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2007-2008 Seminar Series in Electrical Engineering
Winter 2008 (Circuits and Embedded Systems Area)

Lithography Physics, Models and Technology Pathways to 7nm Half-Pitch

Andy Neureuther
UC Berkeley

Wednesday, January 30, 2008 at 1:00PM

54-134 Engineering IV Building
Refreshments Served

Abstract: The physical foundation for optical projection printing will be described and used to examine the technology scaling challenges of pathways to 22 nm with DUV and 7 nm with EUV. The basic phenomena include resolution half-pitch of 0.5 l/NA, depth-of-focus of 0.5l/NA2 and work done on materials by the time-average of . Off-axis illumination with Resolution Enhancement Techniques (RET) can nearly reduce the feature size to 0.25 l/NA but at the price of increased feature type dependencies. Optical Proximity Effects and lens Aberrations produce cross-talk among features to a radius of 3 l/NA and fast-CAD methods can quickly identify locations of worst-case aberration effects in entire circuit layouts. Polarization effects and their compensation by polarizing the illumination are issues for so called high-NA starting at NA of 0.7. Water immersion at 193 improves resolution by the 1.46 refractive index of water and can be viewed as either a wavelength reduction or an NA increase to above unity at 1.4. Gates can be much smaller than the half-pitch due to etch treatments or optical techniques. For grating like regular patterns dominated by interference, the working intensity threshold can be lowered such that feature sizes set by the sharp nulls can be one fourth or less of their 0.5 l/NA periodic separation or 0.125 l/NA. Interleaving two and three patterns in Multiple Patterning and Pitch Division can then increase the pattern density. The 45 nm generation can be done with off-axis immersion at 193 nm, the 32 nm node will require Double Pattering or Double Pitch, and the 22 nm generation might be technically possible with a Double Method or a Triple Method as a back-up. EUV is approaching technical feasibility with 13.3 nm wavelength that is 10 times smaller than 193 nm viewed in water but the maximum numerical aperture is about 0.5. Thus for EUV the 16 nm node would be straightforward, the 11 nm node might require a throughput reduction due to some RET, and the 7 nm node would likely have low throughput due to Double Methods. Resist Recording Materials, are a critical issue for all lithography methods as they have resolution limits and line-width variations that are interdependent with image quality and exposure dose. The choice of an approach will be greatly influenced by the cost-of-ownership and the degree to which equipment manufacturers can control unwanted second order effects in highly optimized tool configurations. Progress will be a matter of integrating the overall complexity of using restricted near grating like patterns through collaboration of circuit designers, device and process technologists and equipment suppliers.

Biography: Dr. Andrew R. Neureuther was born in Decatur, Illinois on July 30, 1941. He received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from the University of Illinois, Urbana, in 1963, 1964 and 1966, respectively as a member of the Antenna Laboratory. Dr. Neureuther joined the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley as a faculty member in 1966 where he is the Conexant Systems Distinguished Professor. His initial research was on integral equation methods for analysis of antennas and diffraction gratings. His main area of research has become computer-aided modeling of lithography and semiconductor fabrication processes. The latter began in 1972 through an industrial leave at the IBM T. J. Watson Research Center to work on photoresist modeling with Dr. F.H. Dill. With Professor W.G. Oldham, he then developed the user oriented computer programs for Simulation And Modeling of Profiles in Lithography and Etching (SAMPLE). The need to understand and control processes in the semiconductor industry provided the motivation, relevant applications and financial support to further extend this work through consortia and projects with the Semiconductor Research Corporation and DARPA. Recently, he also served as Associate Chair of his Department (1996-1999) and as Chair of the Applied Science and Technology Graduate Group (2000-2003). Dr. Neureuther has pioneered modeling and simulation of integrated circuit processing for many physical process effects as well as the use of these tools to explore innovation and manufacturing issues in emerging technologies. His work includes models for chemically amplified imaging materials (STORM), simulation of optical, electron, ion beam and x-ray lithography (SAMPLE), assessment of residual effects of defects and lens aberrations (SPLAT), electromagnetic scattering (TEMPEST), time-evolution of topography (SAMPLE3D), environments for integrating simulators with process flow (SIMPL) and remote web-based simulation (LAVA). Dr. Neureuther is a Fellow of the IEEE. He has published 250 papers and has advised 35 M.S. and 30 Ph.D. students. He was elected to the National Academy of Engineering (1995) and was selected as a Distinguished Alumni by the Electrical and Computer Engineering Department at Illinois (2001). He recently received the IEEE 2003 Cledo Brunetti field award which is given for contributions to miniaturization in electronics.