I was a Ph.D. student in High-Performance Mixed-Mode Circuit Design Group from 2001 to 2007 and my advisor was Professor Ken Yang. I worked at Rambus, Inc. until 2008. Since November 2008 I have been with NetLogic Microsystems, Mountain View, where I design high-speed ADCs.

Here is my latest resume.

 

Aida Varzaghani

Ph.D., Mixed-Mode Circuit Design,

UCLA, 2007

aida.irn@gmail.com

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Research interests

 

  • High-speed, high-performance mixed-mode integrated circuit design, in particular, high-speed ADCs

  • Methodologies for analog circuit design and characterization
Education

 

  • Ph.D., Electrical Engineering (Integrated Circuits and Systems), University of California, Los Angeles, 2001-2007

  • M.S., Electrical Engineering (Electronics), Sharif University of Technology, Tehran, Iran, GPA: 18.33/20, 1999-2001 (honor)

  • B.S., Electrical Engineering (Electronics), Sharif University of Technology, Tehran, Iran, GPA: 18.05/20, 1995-1999 (honor)

 
Publications

 

  • Aida Varzaghani and Chih-Kong Ken Yang, "A 4.8-GS/s 5-bit ADC-based Receiver with Embedded DFE for Signal Equalization," accepted for publication in IEEE Journal of Solid-State Circuits.

  • Azita Emami-Neyestanak, Aida Varzaghani, John Bulzacchelli, Alexander Rylyakov, Chih-Kong Ken Yang and Daniel Friedman, "A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE," IEEE Journal of Solid-State Circuits, vol. 42, pp. 889-896, April 2007.

  • Azita Emami-Neyestanak, Aida Varzaghani, John Bulzacchelli, Alexander Rylyakov, Chih-Kong Ken Yang and Daniel Friedman, "A Low-Power Receiver with Switched-Capacitor Summation DFE," IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 322-325, June 2006.

  • Aida Varzaghani and Chih-Kong Ken Yang, "A 6-GSamples/s Multi-Level Decision-Feedback-Equalizer Embedded in       a 4-bit Time-Interleaved Pipeline A/D Converter,"  IEEE Journal of Solid-State Circuits, vol. 41, pp. 935-944, Apr. 2006.

  • Aida Varzaghani and Chih-Kong Ken Yang, "A 600-MHz, 5-bit Pipeline A/D Converter using Digital Reference Calibration," IEEE Journal of Solid-State Circuits, vol. 41, pp. 310-319, Feb 2006.

  • Aida Varzaghani and Chih-Kong Ken Yang, "A 6GS/s, 4-bit Receiver Analog-to-Digital Converter with Embedded DFE," IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 322-325, June 2005.

  • Aida Varzaghani and Chih-Kong Ken Yang, "A 600MS/s, 5-bit Pipelined Analog-to-Digital Converter for Serial-Link Applications," IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 276-279, June 2004.

  • Aida Varzaghani and Mojtaba Atarodi, "A New Method to Increase the Dynamic Range of Switched OpAmp                 Delta-Sigma Modulators," IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 620–623, May 2002.

 
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