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Wireless Integrated Systems
Research Group
The underlying theme in our work is to successfully bridge
between theoretical and experimental aspects of wireless data
communications.
The research is fundamentally multidisciplinary
in nature and is focused on practical aspects of wireless data
communication systems. The work is divisible into two main thrusts. The
first deals with experimental wireless research, while the second deals
with VLSI for wireless data communications. These are elaborated upon in
the following two sections.
1. Experimental Wireless Data Communications
The scientific method consists of theoretical analysis
followed by experimental validation and feedback in order to refine the
theory. One of the main thrusts of our work since 1999 has been the
identification of practical bounds for high speed wireless communication
systems. The Wireless Integrated Systems Group (WISR) at UCLA has been at
the forefront of experimental wireless data communications. Over the years
we have developed a number of wireless testbeds that have pushed the
envelope in the understanding of the physical limits of broadband wireless
systems. A unique feature of these testbeds is that they incorporate VLSI
ASICs developed as part of the VLSI research also carried out within the
group. The testbeds include:
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2008: Gbps 8x8 MIMO link in the 5 GHz ISM band, featuring WISR group
ASICs
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2007: 4x4 real time MIMO OFDM testbed
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2004: 2x2 non real time MIMO OFDM testbed
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2003: Diversity enabled WCDMA receiver PCMCIA (with Innovics
Wireless)
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2001: Fast Hopping FHSS FSK Testbed with 100 khops
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1998: 30 Mbps M-QAM testbed with real time smart antenna and DFE processing
2. VLSI Systems for Wireless Communications
The
identification of the optimum architecture to realize state of the art wireless
communications algorithms is nontrivial. Our original research in this area
was focused on investigating low power, area efficient architectures that
realize advanced wireless communications concept. In recent years, this has
given way to the development of highly parametrizable and versatile
accelerator cores that can span multiple systems. The work has given rise
to the following ASICs (application specific integrated circuits), all of
which have been fabricated and verified.
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2008: MIMO OFDM Demod
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2007: LDPC Decoder ASIC
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2004: 8x8 MIMO Decoder ASIC
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2003: Universal Rake Receiver ASIC
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2003: Diversity Enabled WCDMA Receiver (with Innovics Wireless)
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2003: High Speed Mobile OFDM Receiver ASIC
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2002: Space-Time Block Decoder ASIC
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2000: mMarsLink: 100 mW FSK Receiver ASIC for the Mars rover
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1999: 100 uW 20 Mcps Versatile Correlator
Chip for
Third Generation WCDMA Systems
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1999: Versatile Beamforming ASIC (VBASIC)
As is evident from the above, the work is
multi-disciplinary, bringing together aspects of VLSI design, RF circuit
design and communication system design in order to design and develop:
· Optimal systems that provide maximal performance with minimal
hardware complexity
· Novel VLSI architectures and ASICs that will enable efficient realization
of hardware intensive wireless communications systems
· High performance prototype testbeds in order to validate and
quantify the performance of wireless systems under actual channel
conditions
One of the requirements for researchers in the WISR
group is that they must have an experimental/hardware element to their
work. The result is a very well rounded researcher that is in touch with
broader systems aspects both from a theoretical as well as a practical
point of view.
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