NSDTG Research Overviews

Research Objectives and Areas of Interest

    After over 5 decades of diligent and innovative research and development efforts to miniaturize electronic devices, power dissipation and fault tolerance now become the two most critical challenges in advancing forward. Together with the ever sought after performance, these three themes constitute the key research objectives in our group. We aim to develop nanostructure devices and technology for the future generation energy efficient, fault tolerant, and high performance integrated circuits and systems. The major research topics include:

Low Dissipation Nanoelectronics

    The power dissipation in the state-of-the-art digital CMOS integrated circuits has become prohibitively high. In order not to exceed the on-chip thermal management capability, the operating frequency in integrated circuits has almost ceased to increase and thereby mandated other circuit architectural and software changes. At the transistor level, the physical origins of the aforementioned dissipation have been well understood. The issue is believed to be exacerbated with the introduction of high mobility channel materials with inherently narrower bandgap. Our group has been investigating approaches to implement low dissipation nanoscale transistors using either novel hetero-structures for selective off-state leakage suppression or new voltage bias schemes to reduce dynamic power consumption. In addition, we are exploring several new structural concepts to improve the practicality of tunneling field-effect transistors, which possess a subthreshold swing less than what the thermodynamic limit would permit to achieve significant power reduction. (The concept shown in the left figure will be presented in ICSICT 2008.)

Graphene Nanostructure Devices and Technology

    Graphene, a single atomic layer of carbon atoms arranged into a 2D hexagonal lattice, has many fascinating yet unique physical and electronic properties. For instance, it is a semi-metal with an almost zero bandgap at room temperature that possesses an extremely high electron mobility of up to 200,000 cm2/V-s at a carrier density on the order of 1013 cm-2. These characteristics could enable devices with high transconductance, intrinsic gain, and cut-off frequencies at low supply voltage for receiver front-end applications. Our group is developing the fabrication technology in demonstrating a revolutionary RF transistor with graphene channel to replace the conventional CMOS. During the modular process developments, we are also focusing on the enabling science such as graphene monolayer deposition selectivity, dielectric nucleation mechanism, and selective etching chemistry etc.

Nanotechnolgy Enabled Fault Tolerant Computing

    Nanoscale devices based on crossed semiconductor nanowires have promising characteristics in addition to providing great density advantage over conventional CMOS. The density advantage could, however, be easily lost when assembled into nanoscale systems and especially after techniques dealing with high defect rates and manufacturing related layout/doping constraints are incorporated. Very recently, Nanoscale Application Specific IC (NASIC) based processors with a variety of built-in fault tolerance techniques have been theoretically demonstrated. Our group is developing the enabling nanotechnology to fabricate the tile-based 2D semiconductor nanowire grid fabrics and cross-point transistors. In particular, we are tackling the fundamental problem of nanowire or nanotube alignment with an intrinsic control of the nanowire or nanotube pitch by fusing the ‘bottom-up’ and ‘top-down’ approaches.

UCLA Infrastructures