|
|||
|
|
|
| |
|
|
|
|
|
|
|
|
|||
|
|
||
|
|
 |
|
 |
|
 |
|
 |
|
 |
|
|
|||||||||
|
|
|||||||||
|
||||||||||
|
|
|||||||||||||||||||||||||||||||||
 |
 |
|
- "A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions," K.-L. J. Wong, A. Rylyakov, and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.41, pp. 881-888, Apr 2007. - "A Study on the Optimal Data Rate for Minimum Power of I/Os," H. Hatamkhani and C.-K.K. Yang, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 53, no. 11, pp. 1230-1234, Nov 2006 - "A 6-GSamples/s Multi-Level Decision Feedback Equalizer Embedded in a 4-Bit Time-Interleaved Pipeline A/D Converter," A. Varzaghani and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.41, pp. 935-944, Apr 2006. - "A 600-MS/s 5-Bit Pipeline A/D Converter Using Digital Reference Calibration," A. Varzaghani and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.41, pp. 310-319, Feb 2006. - "A sub-10-ps multiphase sampling system using redundancy," Li-min Lee, D. Weinlader, and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.41, pp. 265-273, Jan 2006. - "Offset Compensation in Comparators with Minimum Input-Referred Supply Noise," K.-L.J. Wong, and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.39, pp. 837-840, May 2004. - "A 27-mW 3.6-Gb/s I/O Transceiver," K.-L.J. Wong, H. Hatamkani, M. Mansuri, and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.39, pp. 602-612, Apr. 2004. - "Methodology for On-Chip Adaprive Jitter Minimization in Phase-Locked Loops," M. Mansuri, A. Hadiashar, and C.-K.K. Yang, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.50, pp. 870-878, Nov. 2003. - "A Low-power Adaptive Bandwidth PLL and Clock Buffer with Supply-Noise Compensation," M. Mansuri and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.38, pp. 1804-1812, Nov. 2003. - "Jitter Optimization Based on Phase-Locked Loop Design Parameters," M. Mansuri and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.37, pp. 1375-1382, Nov. 2002. - "Fast Frequency Acquisition Phase-Frequency Detectors for Gsamples/s Phase-Locked Loops," M. Mansuri, D. Liu, and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.37, pp. 1331-1334, Oct. 2002. - "A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-um CMOS," C.-K.K. Yang, V. Stojanovic, S. Modjtahedi, M.A. Horowitz, and W.F. Ellersick, IEEE Journal of Solid-State Circuits, vol.36, pp. 1684-1692, Nov. 2001. - CONFERENCE PROCEEDINGS - - "BER-based Adaptation of I/O Link Equalizers," E-H. Chen, J. Ren, J. Zerbe, B. Leibowitz, H. Lee, V. Stojanovic, C.-K.K. Yang, in IEEE Symposium on VLSI Circuits Digest of Technical Paper, June 2007, to appear- "Precursor ISI Reduction in High-Speed I/O," J. Ren, H. Lee, Q. Lin, B. Leibowitz, E-H. Chen, D. Oh, F. Lambrecht, V. Stojanovic, C.-K.K. Yang, J. Zerbe, in IEEE Symposium on VLSI Circuits Digest of Technical Paper, June 2007, to appear - "Adaptive Low-Jitter LC-Based Clock Distribution," L-M. Lee, C.-K. K. Yang, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2007 - "Power-Centric Design of High-Speed I/O ," H. Hamtamkhani, F. Lambrecht, V. Stojanovic, C.-K.K. Yang, in 43rd Design Automation Conference Digest of Technical Paper, July 2006 - "A Low-Power Receiver with Switched-Capacitor Summation DFE," A. Emami-Neyestanak, A. Varzaghani, J. Bulzacchelli, A. Rylyakov, C.-K.K. Yang, D. Friedman, in IEEE Symposium on VLSI Circuits Digest of Technical Paper, June 2006 - "A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decision," K.-L.J. Wong, A. Rylyakov, C. -K. K. Yang, in IEEE Symposium on VLSI Circuits Digest of Technical Paper, June 2006 - "An 8Gb/s Transformer-Boosted Transmitter with >VDD Swing," J. Kim, H. Hatamkhani, C. -K. K. Yang, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2006 - "A Serial-Link Transceiver with Transition Equalization," K. Wong, C.-K.K. Yang, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2006 - "A broadband 44-GHz frequency divier in 90-nm CMOS, K. Wong, C.-K.K. Yang, in Compound Semiconductor Integrated Circuit Symposium, Nov. 2005 - "A 6GS/s, 4-bit Receiver Analog-to-Digital Converter with embedded DFE," A. Varzaghani, C.-K.K. Yang, in IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2005. - "A Sub-10ps Multi-Phase Sampling System Using Redundancy," L-M. Lee and C.-K.K. Yang, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2005. - "Techniques for Improving the Accuracy of Geometric-Programming Based Analog Circuit Design Optimization," J. Kim, J. Lee, L. Vandenberghe, and C.-K.K. Yang, in Proceedings of International Conference on Computer Aided Design (ICCAD) 2004. - "Power Analysis for High-Speed I/O Transmitters," H. Hatamkhani,C.-K.K. Yang, in IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2004. - "A 600MS/s, 5-bit Pipelined Analog-to-Digital Converter for Serial-Link Applications," A. Varzaghani, C.-K.K. Yang, in IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2004. - "Evaluation of fully-integrated switching regulators for cmos process technologies," Jaeseo Lee, G. Hatcher, L. Vandenbergh, and C.-K.K. Yang, in proceedings of International Symposium on System-on-Chip, 2003. Nov. 2003, pp. 155 - 158. - "CMOS LC oscillator using variable mean frequency," Ping-Hsuan Hsieh, J. Judy, and C.-K.K. Yang, in Proceedings of IEEE Custom Integrated Circuits Conference, Sept. 2003, pp. 147 - 150. - "Analysis of timing recovery for multi-Gbps PAM transceivers," Chih-kong Ken Yang and Koon-lun Jackie Wong, in Proceedings of IEEE Custom Integrated Circuits Conference, Sept. 2003, pp. 67 - 72. - "A 27-mW 3.6-Gb/s I/O transceiver," K.L.J. Wong, M. Mansuri, H. Hatamkhani, and Chih-Kong Ken Yang, in IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2003, pp. 99 - 102. - "A 10-mw 3.6-Gbps I/O transmitter," H. Hatamkhani, K.-L.J. Wong, R. Drost, Chih-Kong Ken Yang, in IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2003, pp. 97 - 99. - "A Low-power Low-Jitter Adaptive-Bandwidth PLL and Clock Buffer," M. Mansuri and C.-K.K. Yang, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2003, pp. 430-440. - "Jitter Optimization Based on Phase-locked Loop Design Parameters," M. Mansuri and C.-K.K. Yang. in IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2002, pp. 138-142. - "Fast Frequency Acquisition Phase-Frequency Detectors for GSa/s Phase Locked Loops," M. Mansuri, D. Liu and C.-K.K. Yang. in IEEE European Solid-State Circuits Conference Digest of Technical Papers, Sep. 2001. - BOOK CHAPTERS, TALKS, ETC - 1. "Delay-locked loops -- an overview," in Phase-locking in High Performance Systems (B. Razavi, editor), IEEE Press, March 2003.2. "Circuits for High-Performance I/O," C.-K. Ken Yang, ch. 31 in Computer Engineering Handbook (V. Oklobdzija, editor). CRC Press, December 2001 3. "High Speed Electrical Signaling," C.-K.K. Yang, S. Sidiropoulos and M. Horowitz. Ch. 16 in Design of High-Performance Micropocessor Circuits (A. Chandrakasen, F. Fox and W. Bowhill, editors) - THESIS -
| |||||||||||||||||||||||||||||||
|
We publish papers on various kinds of cutting-edge mixed-mode circuit designs in sub-micron CMOS. Journal Papers Conference Proceedings Book Chapters, Talks, etc. Thesis of group people |
|
|
|
||||||||||||||||||||||||||||||
|
|
|
|
|
|
|||||||||||||||||||||||||||||
|
|
|
|
 ::
UCLA::
EE Dept.
Last Modified Apr. 7th, 2007.
|
©
2004 CKY Group |