- LOW-POWER HIGH-SPEED I/O - > "A Low-power Adaptive Bandwidth PLL and Clock Buffer with Supply-Noise Compensation," M. Mansuri and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.38, pp. 1804-1812, Nov. 2003. > "Jitter Optimization Based on Phase-Locked Loop Design Parameters," M. Mansuri and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.37, pp. 1375-1382, Nov. 2002. > "Fast Frequency Acquisition Phase-Frequency Detectors for Gsamples/s Phase-Locked Loops," M. Mansuri, D. Liu, and C.-K.K. Yang, IEEE Journal of Solid-State Circuits, vol.37, pp. 1331-1334, Oct. 2002. > "A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-um CMOS," C.-K.K. Yang, V. Stojanovic, S. Modjtahedi, M.A. Horowitz, and W.F. Ellersick, IEEE Journal of Solid-State Circuits, vol.36, pp. 1684-1692, Nov. 2001. > "CMOS LC oscillator using variable mean frequency," Ping-Hsuan Hsieh, J. Judy, and C.-K.K. Yang, in Proceedings of IEEE Custom Integrated Circuits Conference, Sept. 2003, pp. 147 - 150. > "Analysis of timing recovery for multi-Gbps PAM transceivers," Chih-kong Ken Yang and Koon-lun Jackie Wong, in Proceedings of IEEE Custom Integrated Circuits Conference, Sept. 2003, pp. 67 - 72. > "A 27-mW 3.6-Gb/s I/O transceiver," K.L.J. Wong, M. Mansuri, H. Hatamkhani, and Chih-Kong Ken Yang, in IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2003, pp. 99 - 102. > "A 10-mw 3.6-Gbps I/O transmitter," H. Hatamkhani, K.-L.J. Wong, R. Drost, Chih-Kong Ken Yang, in IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2003, pp. 97 - 99. > "A Low-power Low-Jitter Adaptive-Bandwidth PLL and Clock Buffer," M. Mansuri and C.-K.K. Yang, IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2003, pp. 430-440. > "Jitter Optimization Based on Phase-locked Loop Design Parameters," M. Mansuri and C.-K.K. Yang. IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2002, pp. 138-142. - HIGH-SPEED DATA CONVERTER - - MIXED-MODE SIGNAL CIRCUIT OPTIMIZAITON - > "Evaluation of fully-integrated switching regulators for cmos process technologies," Jaeseo Lee, G. Hatcher, L. Vandenbergh, and C.-K.K. Yang, in proceedings of International Symposium on System-on-Chip, 2003. Nov. 2003, pp. 155 - 158.
			We publish papers on various kinds of cutting-edge mixed-mode circuit designs in sub-micron CMOS. Low-power High-speed I/O High-speed ADC Mixed-mode signal circuit optimization Click here to sort in chronological order.

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