- LOW-POWER HIGH-SPEED I/O - |
In this research we focus on high-speed I/O circuit design. The project is generally separated into three main parts: Transmitter, receiver, and clock generattion. Power optimization is done within each part. Analysis and modeling is being developed so as to achieve the optimization. Adaptive circuitries including adaptive channel equalization and process and supply noise insensitive circuits are being examined as well.
- HIGH-SPEED DATA CONVERTER -
Recent Multi-Gbps serial transceiver scheme tends to employ multi-level modlution to overcome the frequency-selectivity of the channel. Anlog-to-digital converters that operate at multi-Gsa/s with low-to-medium resolution(4-6bits) and large bandwidth(multi-GHz) have been of great interest for these serial link transceivers. In this research, we focus on the design and optimization of high-speed data converter as well as various signal processing techniques that can further extend the speed and accuracy of the data converter.
- MIXED-MODE SIGNAL CIRCUIT OPTIMIZATION -
Ever-continuing technology scaling enables the billions of transistors to be integrated, but at the same time complicated physical characteristics of the sub-micron transistors makes the mixed-mode signal circuit design a quite challenging task in today's technology. In this research, we explore various mathematical methods in the design and optimization of various mixed-mode signal circuits.
We are conducting interesting research projects on various mixed-mode circuit designs. Current researches majorly focus on
:: Low-power high-speed I/O design
:: High-speed data converter design
:: Mixed-mode signal circuit optimization
|:: UCLA:: EE Dept. Last Modified Feb. 26th, 2004.||© 2004 CKY Group|