EE115C: Digital Electronic Circuits
Software
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Prof. Dejan Markovic Cadence Design Tools and 90nm GPDK Technology Winter 2007 |
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Starting in Winter 2007, Cadence design tools will be used in EE115C class. Cadence is a one-stop solution for schematic capture, physical layout, parameter extraction, and design verification. It is widely used tool-set in industry and academia.
Advanced 90nm technology will be used in class to illustrate basic principles and provide insight into realistic parameters of today's digital circuits (delay, power, transistor size, etc). The general process design kit (GPDK090) from Cadence has 9 layers of metal (picture on the right illustrates the stack of metal layers in a real life processor design).
This material supplements the class eeweb page. The objective is to provide necessary training in tools needed for simulation, layout, and verification of digital circuits. The skills acquired in the tutorials will be applied to homework and project assignments.
How to use this page: There are two principal ways you can go about learning Cadence tools: from the design flow aspect, or from the task-oriented aspect. Both paths cover identical material. |
Cross-section of a 64-bit high-speed processor in a 90nm technology. (Courtesy: IBM) |
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This path takes you through various steps of the flow that include schematic and layout entry, design verification, and simulation. Each of these tasks can be treated as a separate module. |
This path usually combines several steps of the flow path in order to demonstrate some circuit design task such as generating MOS IV characteristics or technology calibration of FO4 and ring oscillator delay. |
Finally, if you would like to refresh on some particular skills such as schematic or layout editing, there is the help and how-to page which summarizes basic editing and tool setup procedures. |
Last Modified on January 1, 2007 by Dejan Markovic |
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Electrical
Engineering