EE115C:  Digital Electronic Circuits                  Cadence Tutorials                           Electrical Engineering

 Prof. Dejan Markovic                            #2:  Hierarchical Schematic and Simulation                                      Winter 2007

                                                                                                                    tutorials | main page | feedback

The objectives are to become familiar with Virtuoso schematic editor, learn how to create the symbol view of basic primitives, compose symbols hierarchically, and verify the design through simulation.  In order to achieve these objectives, CMOS inverter in a fanout-of-four (FO4) and ring oscillator configurations is considered.  These configurations are widely used as formalism for technology characterization: to estimate the speed of technology in terms of gate delay.  The numbers obtained here will thus become essential tool in estimating delays of complex circuits.

Start up Cadence tool and open Library Manager window.  If you don’t remember all the steps, review Starting up Cadence and Entering Design Schematic sections from Tutorial 1.

Entering Design Schematic

We are going to create the inverter sized for unit drive strength (typically indicated as “1x”).  In the Library Manager, click to select ee115c library and then click File > New > Create cellview to create schematic view for the new cell. 

Type INVX1 in the Cell Name field as illustrated.

Click OK.

After you click OK, Virtouso Schematic Editing window will pop up.

Instantiate NMOS and PMOS transistors as described in Tutorial 1, section Entering Design Schematic.  The unit (“1x”) inverter has W_p/W_n ratio of around 2, where W_n is 2x the minimum width.  In our technology, W_min = 120nm, so the unit inverter is W_p/W_n = 480nm/240nm.  Your schematic editor window should look like this:

Next, we are going to add input and output pins, which are needed to describe connectivity information for the symbol view.  To instantiate a pin, type “p” in the schematic editor and following dialog will show up:

Type A VDD GND under Pin Names to define input pins, click Hide and place the pins in the schematic (in the order you specified).

Follow the same procedure to place output pin Z.

Wire up the schematic (reminder: press “w” to enter wiring mode / Esc to exit).  The final schematic should look like this (type “f” to fit the drawing to page):

Click Design > Check and Save or type “X” to check and save the design.  Watch the CDS.log window for any potential warnings.  In the log window, you should see following messages:

        Schematic check completed with no errors.

        “ee115c INVX1 schematic” saved.

Creating Symbol View

The symbol view can be created directly from the schematic view of the cell.  In Virtuoso schematic editor, click on the Design menu and choose Create Cellview > From Cellview and select from schematic to symbol view as shown in the pop-up window below.

After you click OK, the following window will appear indicating that input pins A GND and VDD will be placed on the left and that output pin Z will be placed on the right:

Click OK and the default box-shaped symbol view is created as shown below:

Next, we are going to modify the shape of this symbol view in order to represent the inverter with the familiar shape (triangle + bubble) used by digital designers.  In the Virtuoso Symbol Editing window, go to Add menu and select Shape > Line to add lines (you can also find a short-cut to this feature along the left banner under the Tools), or Shape > Circle to create the bubble at the output of the inverter.  You can also drag the pins around to position VDD and GND to top and bottom, respectively, and move labels and lines around to modify the symbol.  Your final symbol view should look something like this:

Edit properties (reminder: select the object and press “q”) of the [@partName] label and specify justification to centerLeft as shown in the dialog box below.  This will ensure that the INVX1 label is nicely aligned within the shape (as you are going to see in the next section).

When you save the final version, make sure it is bug-free.  As in the schematic entry, check the CDS.log window.  It should display following message for the correctly designed symbol view:

        “INVX1 symbol” saved.

Now we can instantiate this symbol to build other circuits such as ring oscillator and fanout-of-four (FO4) test circuit.

Hierarchical Design: Ring Oscillator

By now you are already an expert in creating new cells, so let’s make another one.  Go to the Library Manager window and add Ring_OSC cell to your ee115c library.

We are going to create a 15-stage ring oscillator in order to measure the delay of the 1x inverter.  In the Virtuoso Schematic Editor window, now instantiate INVX1 cell (symbol view) from your ee115c library.  Furthermore, we are going to place the 15 inverters in three rows, 5 in each row, to make the schematic easily readable.

To place the first row of cells, in the Array field specify 5 columns (meaning you want to place 5 instances in a column-like fashion).

Click Hide (or press Enter) and place the first instance.

Then move the mouse pointer over to the right to define the location for other instances.  You should see yellow flylines as follows:

The first row of instances should look something like this:

For easy routing of global signals VDD and GND, we are going to flip and rotate the second row of cells.  In the Add Instance menu, specify again 5 columns, but also click once on Sideways and Upside Down buttons.  Finally, create the third row in the same way the first row was created and place the third row below the second row.  The final placement should look like this:

Instantiate vdd and gnd cells from analogLib and wire up the schematic (reminder: press “w” to enter wiring mode / Esc to exit).  

Also label one of the points in the ring – this point will be used as a test point to measure the delay.  You can either execute 

Add > Wire Name from the drop down menu or press “l” (small “L”) to add the label.  Add label named TP and place it at the output 

of the last inverter in the first row.

The final schematic should look like this:

Ring Oscillator Delay Simulation

Invoke simulation environment by choosing File > Analog environment from the Virtuoso schematic editor window.

(review Spectre Simulation section of Tutorial 1 if needed)

In addition to the setup in Tutorial 1, we also need to set up global source such as vdd!.

In the Analog Design Environment, Click Setup > Stimuli...

Click on Global Sources

The following dialog window will pop up.  Make sure vdd! is hightlighted.

Click on Enabled

Enter 1.0 in DC voltage.

Then Click the Change botton.

Click OK.

Set up the models, select transient analysis with duration of 1.5ns and moderate accuracy.

Select TP as the output to be plotted.

You should get the following graph as the simulation result.

Now, let’s calculate the oscillation period.  Click on calculator button as highlighted above.  In the Calculator window (shown below), select tran tab and vt under Selection choices.  Then click on delay, Virtuoso Schematic Editor window will pop up for you to select the waveform you want to probe: select TP and go back to the Calculator window.  It should look like this:

Both Signal1 and Signal2 fields should read VT(“/TP”).  Set Threshold Value 1 to 0.5 (V_DD/2=0.5V) and Edge Number 1 to rising (falling is also OK).  Click on the >>> button to specify the second trigger point.  Specify parameters as indicated below:

Click on the >>> button to calculate the delay between the first and the second rising edge of signal TP.  Click OK, the following window will appear.

Click Eval button to evaluate the delay expression highlighted above.  The expression evaluates to 400ps as shown below.

This is the period of oscillation.  In terms of gate delay, period T has a total of 15 low-to-high and 15 high-to-low transitions.

                        T = N∙(t_pLH + t_pHL),  where N is the number of stages (N=15)

                        Gate delay = t_p = (t_pLH+t_pHL)/2

Therefore:          t_p = T/2N

                        For N = 15:  tp = 400/30 = 13.3ps

This is the delay of an inverter which output is loaded with an identically sized inverter.  This is also called the delay of a fanout-of-one (FO1) inverter.  In circuits optimized for speed, typical fanout is about 4, so designers often times use fanout-of-four (FO4) inverter as normalization unit to compare the quality of their designs.  It is therefore of interest to evaluate FO4 delay for our technology.

Note: it is a good idea to save the simulation settings in a state file.  (reference: check Spectre Simulation section of Tutorial 1 on how to do this)  

Save the state in file:  state_Ring_OSC.

Hierarchical Design: FO4 Inverter

The FO4 test circuit example will use two levels of hierarchy: the circuit will be composed of three stages, each stage being composed of inverters and capacitors.  To save time and also learn how to port over cells from other libraries, we are going to copy over FO4_inv_stage cell from ee115c public repository.

Position yourself in the following directory:

        <disk_path><user_name>/ee115c/cadence-labs/ee115c

        (example:  /w/fac.01/ee/dejan/ee115c/cadence-labs/ee115c)

Create new folder for the new cell:

        > mkdir FO4_inv_stage

Copy cell FO4_inv_stage from /usr/public.2/ee115c/ directory into the local folder:

        > cp -R /usr/public.2/ee115c/cadence-labs/ee115c/FO4_inv_stage/* FO4_inv_stage/

In the Library Manager window, select View > Refresh.  The following window will pop up:

Click None because you don’t want to contaminate your library with what someone else did.  We are going to be cautious and fix the missing links later.  Click OK and you will see that cell FO4_inv_stage is now part of your ee115c library.

Let’s now try to open schematic view.  The following window will pop up:

This tells us that the INVX1 cell used to create FO4_inv_stage cell was referenced from some other library, in this case this library was named ee115c_lab1.

Click Close.

The following schematic will appear (notice broken links for the INVX1 instances).

We are now to substitute INVX1 cells with the INVX1 cell that we designed earlier in this tutorial.  Edit properties for all the invalid objects and change Library Name from ee115c_lab1 (as shown below) to ee115c.

After some touch-up re-positioning and re-wiring of objects, the schematics should look like this:

(you can also open symbol view to see how it looks or wait until a bit later – we are going to use it soon anyway…)

Details of this circuit will be explained in class.

Now, let’s create FO4_inv cell to simulate the delay of FO4 inverter for this technology.  (reference: Entering Design Schematic section of this tutorial explains how to create a new cell)

Instantiate three instances of FO4_inv_stage cell (you are already a master of hierarchical design, so remember to use Array property when adding instances) and connect them together.  Also instantiate these cells from the analogLib and specify their properties as follows:

After placing and wiring components, labeling in and out, your schematic should look like this:

FO4 Inverter Delay Simulation

Invoke simulation environment by choosing File > Analog environment from the Virtuoso schematic editor window.  

(review Spectre Simulation section of Tutorial 1 if needed)

By now you have learned to save the state.  Save this state in file:

        ~/ee115c/cadence-labs/.artist_states/state_FO4_inv.

Netlist and run, the simulation will produce the following waveforms (review Tutorial 1 for instructions about adding labels):

You can also save this graph using the menu bar...

Now, we can measure the low-to-high and high-to-low delay values.  Remember (as discussed in class) that, by convention, the low-to-high or high-to-low delays are defined with respect to the output transition.

Low-to-high transition (i.e. in falling, out rising)

Invoke Calculator (refer to the Ring_OSC example in this tutorial on how to do this) and specify parameters as shown below:

Click the >>> button and specify parameters for the rising transition at the output:

Click the >>> button and then the OK button, the delay expression will appear:

Evaluate this expression:

Therefore:    t_pLH = 37.1ps

High-to-low transition (i.e. in rising, out falling)

In the Calculator window, we can simply type in the expression for t_pHL (refer to the t_pLH calculator expression and swap “rising” and “falling”)

We get:    t_pHL = 30.5ps

Therefore:

Schematic Editor: Zooming In

There are several methods for zooming found in the View menu.  One easy way to zoom to the exact region you want is by using the zoom hot key.

• Type “z”. This puts you in zoom mode. Note that the cursor has changed.  Next hold down the left mouse button and "drag" out a box which surrounds the region you wish to zoom to.  When you release the mouse the screen will zoom to where your box was.

• If you mess up don't panic. Remember, “f” will always zoom to fit.

The hotkey “]” can be used to zoom out by a factor of two.

The hotkey “[“ can be used to zoom in by a factor of two.

Last Modified on December 23, 2006 by Dejan Markovic