EE115C:  Digital Electronic Circuits                  Cadence Tutorials                           Electrical Engineering

 Prof. Dejan Markovic                               #3:  Virtuoso Layout Editing (DRC, LVS)                                        Winter 2007

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The objectives are to become familiar with Virtuoso layout editor, the design rule checking (DRC), and layout versus schematic (LVS) verification process.  The concepts will be demonstrated on INVX1 cell from Tutorial 2.  Other gates can be viewed as relatively simple extensions of the inverter.

Starting Virtuoso Layout Environment

In the Library Manager, click to select ee115c library, select INVX1 cell and then click File > New > Create cellview to create the layout view for the INVX1 cell.

Type layout in the View Name field and select Virtuoso Tool.

Click OK.

After you click OK, Virtouso Layout Editing window will pop up.

On the very top of the window the title bar should say

        “Virtuoso® Layout Editing: ee115c INVX1 layout”

This means that you are editing layout view of INVX1 cell from ee115c library.

Next, across the top you should see the menu bar which contains the following menu items: Tools, Design, Window, Create, Edit, Verify, Connectivity, Options, Routing and Assura. These are pull-down menus much like any PC or Mac application.  At the bottom of the window is the Virtuoso Message Area.  It is activated when some work is in progress describing the task being performed. It can say something like “Select the figure to be stretched…”.  The Virtuoso Message Area is a sort of mini-help feature.

The Palette

Additionally, the LSW palette window pops up.

The LSW window is the Smart Palette.

The Smart Palette provides many features.

• It controls which layers are visible, 
  and lets you choose layers for "painting".

• It gives feedback on what is currently under the cursor, 
  and what is currently selected.

It allows you to control which layers can be selected.

Layout Layers

Description of various mask layers can be found at:

        /usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/stream/streamLayer.Map

Note: you can access this file only from your Unix account.

Use only drawing (dg) layers for drawing transistors.

Similar to creating the schematic view of INVX1, we are going to instantiate the layout views of NMOS and PMOS transistors.  In the Virtuoso Layout Editing window, click “i” to instantiate a component.  In the Create Instance pop-up window, click Browse to select a library cell.

Select gpdk090 library,

nmos1v cell,

layout view.

Click Close.

This will take you back to the Create Instance window.

Specify width of 240nm.

Click Hide.

Place the NMOS in the layout.  To do this, just as in the schematic editing, position your cursor in the Virtuoso window where you want your NMOS device placed and left-click, then move the cursor away (yellow box will appear) and press “Esc” key to exit Add Instance mode (yellow box will disappear).

Add instance of a PMOS that is 480nm wide.

This will be your layout editing window.

In the layout, you will only see frames of the layout cells.  Let’s fix this:  from the Virtuoso Options menu, choose Display and set Display Levels to 10.  Before you click OK, let’s take a more detailed look at this form. 

Virtuoso works with the 

placement grid, which is 

specified in the Grid Controls menu.  In our case, the objects are placed on a 5nm grid.  Generally, the grid is about 5-10% of the minimum feature size (90nm for our technology).

In the Display Controls, you can selectively choose which objects will be visible in the layout.

Now click OK.

Now you can see mask layers in the transistor instances as shown below.  Another way to view and hide hierarchical layers is to use shortcuts:  Ctrl-f for hide, Shift-f for display.

Zooming In/Out

As you continue working with Virtuoso Layout Editor, you will often find useful to Zoom parts of your layout.  To Zoom In/Out, you can select options from the Window > Zoom menu or simply remember these useful hotkeys:

Transistor Layers

The NMOS transistor (Zoom In if you need a closer look) is made from following layers:

Similarly, the PMOS is composed from following layers:

You can read more about basic device layout rules in the gpdk090 design rule manual (DRM), which is available in the gpdk090 documentation:

        /usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/docs/gpdk090_DRM.pdf

Now let’s complete layout for INVX1 cell.  To do that, we need to add several objects:

            prBoundary     place and route boundary for cell placement & routing

            n-well              for PMOS transistors (we are working with an “n-well process”)

            power and ground rails

            substrate contacts

            input/output contacts/pins

Before we place all the layers above, these are the rules we are going to use for this technology:

            Metal track      typically about 6 “lambda”                 0.3µm

            Cell height       typically about 10-12 metal tracks      3.6µm

            Power rails      typically about 10 “lambda”               0.6 µm

Let’s first define cell boundary.  Select prBoundary drw layer from the LSW palette window.  Click on the Rectangle button on the left banner menu in the Virtuoso layout window.  Left-click and drag the mouse pointer to define the cell boundary.  It is often conventient to edit properties of the placed object to precisely define its size.

This essentially defines the cell boundary that is 1.8µm wide and 3µm tall, with 0.3µm offset at the bottom (which will be used for the ground power rail).

Next, select the Nwell drawing layer and define the n-well that starts from the middle of the cell (Y=1.8µm) and extends 0.3µm over the cell boundary on top.  Your layout should now look like this:

Design Rule Checking (DRC) using Assura

As part of usual layout design experience, you will often need to perform design rule checking (DRC) to make sure that your design satisfies manufacturing rules.  Let’s do a DRC check on the above layout.  Choose Assura > Run DRC…, the following window will pop-up:

Specify Rules File as:

        /usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/assura/drc.rul

(remember: all technology-related files reside in the public folder under ee115c/cadence-labs)  While it would be easier if you create local copies of the rules files and such, it is a good practice to learn how to work with a centralized database.

Click OK to star the Assura DRC check.  During the run, following window will appear:

You can click Watch Log File… to monitor the DRC progress.

After the run is complete, you will have another pop-up window.

Click Yes to see the final report.

The Error Layer Window will appear:

As you can see, there are several errors being reported.  For each error listed, the number in square brackets indicates how many errors of this type occurred, followed by the description of error.  You can scroll the errors by using arrows on the right.  At the same time, if you look at your Virtuoso layout window, errors will be highlighted as you scroll.  For example, the first out of four errors indicating violation of METAL1.A.1 rule is highlighted in the layout below.

This error in particular says that the minimum metal1 area cannot be less than 0.07µm².  To verify the size of the highlighted metal1 object, we can measure the object size using ruler.  The ruler is invoked with shortcut key “k”.  (all ruler marking can be deleted with “K”)

The size of the metal1 object is 0.24 x 0.12 = 0.0288µm², which violates the rule.  To get more information about the error, in the 

Error Layer Window choose View > Explain, and then click on the highlighted object in layout.  Marker text window will 

show up providing details about the highlighted error.

Explanation of the design rules can also be found in the gpdk090 technology documentation:

        /usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/docs/gpdk090_DRM.pdf

A Note about Assura

Assura is a physical verification tool from Cadence.  It replaces old tool Diva, which used to work well for technologies up to 0.18µm node.   For the deep sub-micron technologies below 0.18µm such as our 90nm technology, Assura provides more accurate results than Diva, particularly in parasitic extraction.  The Assura extraction is based on advanced 3D transistor-level parasitic R and C extraction.  In terms of CAD database, Assura can replace Diva for the Cadence design framework II (DFII) database, versions 4.4 and later.  Unlike Diva which is a flat verification tool, Assura offers hierarchical verification capability.

For information and help pages, invoke cdsdoc from your Unix command prompt and open:

        Assura DRC/LVS > Physical Verification User Guide

The manual is the reference to Assura and it contains lots of information that you will not find in this simple tutorial.

Layout Editing: Wiring Basics

Back to our layout DRC check…  After completing the layout, the kinds of errors we’ve seen naturally disappear.  So, let’s continue.  Close the Error Layer Window (File > Close ELW) and go back to the Virtuoso Layout Editing window.

Add metal1 power rails 0.6µm tall and 1.8µm wide

(reminder: this is the procedure for creating a metal1 filled polygon)

- select Metal1 drawing layer from the LSW window,

- click on the Rectangle button in the Virtuoso Layout Editing window,

- and define the object in layout,

- edit properties if needed

Place the power rails at the top and the bottom of the cell.  The power rails will be shared among adjacently placed cells, so the rails overextend the cell boundary by 0.3µm for the purpose of cell abutment in the vertical direction.  This is also the reason why the power rails span the entire cell width (abutment in the horizontal direction).  Your layout should look like this:

A Bit More Advanced Wiring (Create Path)

Another way to simply wire up the objects is to use Create Path command.  Select the layer from the LSW window (e.g. Poly), go to the Virtuoso Layout Editing window and select Create > Path (or use keyboard shortcut “p”).  Click on the first object you need to route and move the cursor toward the second object.  It should look like this:

Double click on the destination to finish the wire. 

Caveat: you need to click in the middle of the wire in order to keep the lines nicely aligned.  Zoom in around the starting or end point to check if the new wire is nicely aligned with the existing Poly lines.

In other words,

you don’t want to start like this

but, rather, like this

Connect the source terminals to the ground rails, connect the drain terminals together.  Your layout should look like this:

Assume now that the output of a gate (which is in Metal1) drives the input of this gate.  For ease of cell-to-cell routing, we are going to expose the input in metal1 layer.  In order to do that, we need to create Poly-to-Metal1 contact inside the cell.  In other words, we are going to change layers during routing.

Advanced Wiring (Create Path & Changing Layers)

To enable the option of changing layers within Create Path command, in the CDS.log window, select 

Options > User Preferences and check Options Displayed When Commands Start.  

We are going to temporarily enable this option until we finish multi-layer routing.

Select Poly drawing layer from the LSW window and press “p” to create a path.  Notice that now you get a pop-up window like this:

Now start your path from the middle of the Poly and move the cursor toward left.  To go from Poly up to Metal1, simply change the layer in the Create Path menu to Metal1.  When you get back to your layout, you will see that the tip of the wire turns into a contact, which you can place.  Now you can continue to draw your path in the new layer.

To illustrate the above procedure,

click to place the contact 

and continue wiring in Metal1

Double-click to finish the wire.  Your layout should look like this:

We are done with multi-layer routing, so let’s disable this feature.  In the CDS.log window, go to Options > User Preferences and disable Options Displayed When Commands Start.

Creating Substrate Contacts

Now, let’s create substrate contacts.  It is generally recommended to place a few contacts in the power lines, so we are going to add two contacts for the inverter cell (complex gates may require more).  To create a contact, you can select Create > Contact… from the

Virtuoso Layout Editing window or use shortcut “o”.

Select M1_PSUB as Contact Type to connect the p-substrate.

Click Hide and place two contacts.

To keep the cell symmetric, edit contact properties and place them at following locations:

Origin: 

X = 0.45;  Y = 0.3

Another contact:

Origin:  

X = 1.35;  Y = 0.3

Place two Metal1 to n-well contacts (M1_NWELL) and place them at the same X = 0.45 and 1.35 and Y = 3.3.  Your layout should look like this:

Creating Pin Labels

There is one last thing before we are finished with our INVX1 gate.  It would be very useful to add pins with text labels on our layout.  To add a pin with a text label select Create > Pin... from the Virtuoso Layout Editing window.  Shortcut for this is Ctrl-p.  In the pop-up window type the names of the pins and select shape pin, new pop-up window will appear:

Type VDD GND A Z in the 

Terminal Names field.  

(these are pin names 

from the schematic)

Click Display Pin Name to 

display pin names.

Continue with steps 1-3 above to create other pins in the specified sequence (VDD GND A Z).  If the pin text is too large you can bring up the property editor and adjust the height.  Good height for the power pins is 0.2, 0.1 for the signals.  Make sure the direction of pins in the layout matches that in the schematic (e.g. VDD and GND are input pins).

Your final layout should look like this:

You have just finished your custom layout cell.  Before we say congrats on the layout well done, we need to run the final DRC check to make sure the design is DRC-clean!

Invoke Assura DRC check one more time.  If you have done everything correctly, your design should be DRC-clean and you should get the following message:

Layout Versus Schematic (LVS) Check using Assura

As you can see, we still can’t declare complete victory… We also have to verify that the layout we just designed matches the schematic created in Tutorial 2.  This verification is accomplished by checking Layout Versus Schematic (LVS) rules in Assura.

In Virtuoso Layout Editing window, invoke Assura > Run LVS…  The following pop-up window will appear:

Make sure the settings in the Schematic Design Source and the Layout Design Source are set as shown above.  Also, double check that the Extract Rules and the Compare Rules are the following:

        /usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/libs.cdb/gpdk090/extract.rul

    /usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/libs.cdb/gpdk090/compare.rul

Delete the Switch Names field.  Click OK to start the LVS run.  The LVS environment is similar to the DRC environment.  You can also monitor the progress of your LVS run:

Choose to Watch Log File…

Click OK.

After the LVS run is finished, you should see the following pop-up window:

The LVS Debug window will appear (in case you need it for debugging).

Our INVX1 design is now complete.

Last Modified on December 24, 2006 by Dejan Markovic