EE115C:  Digital Electronic Circuits                  Cadence Tutorials                           Electrical Engineering

 Prof. Dejan Markovic                   #6:  Advanced Simulation using OCEAN Environment                              Winter 2007

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This tutorial is a step-by-step procedure for simulating the critical-path delay and energy of your adder design.  The test bench consists of your design wrapped around with the test interface circuits.  The test interface circuits consist of driving stage (buffer) and load gates (16x inverter terminated with a 100fF capacitance that suppresses Miller kick-back).

Step 1:  Schematic Entry

First, we need to create a schematic of an 8-bit adder in Cadence and produce Spectre netlist.  In order to ensure compatibility with the test interface circuit, adhere to the following notation:

            Cell name:

  my_adder_8bit

Input pins (19):

  A0 A1 A2 A3 A4 A5 A6 A7

  B0 B1 B2 B3 B4 B5 B6 B7

  Cin

  GND VDD

Output pins (9):

  S0 S1 S2 S3 S4 S5 S6 S7

  Cout

Step 2:  Netlist Generation

Generate the netlist

Analog Design Environment > Simulation > Netlist > Create

Step 3:  Workspace Setup

In the terminal window, set up the following directories and files:

Copy the following files from ee115c public repository:

            cp /usr/public.2/ee115c/cadence-labs/test_bench.tar .

Unpack the files:

tar –xvf test_bench.tar

Copy the netlist generated in Step 2 into the netlist named test_circuit:

            cp <netlist-path>/my_adder_8bit/spectre/schematic/netlist/netlist test_circuit

If test_circuit_sub exists, remove it:

            rm test_circuit_sub

Merge the simulation files:

      cat test_circuitHeader test_circuit test_circuitFooter > test_circuit_sub

Prepare the files for simulation:

     cat test_circuitHeader test_circuit test_circuitFooter > test_circuit_sub

Step 4:  Simulation Run

Simulation can be executed from the command line or interactively.  The interactive mode allow inspection of intermediate steps (this option is mainly interesting for user-controlled waveform display).

Option A:  fully automated path

Option B:  Interactive mode

You may run simulations from the command line:

ocean < oceanScript.ocn

This commands runs a transient simulation on your netlist, applying the test vectors that exercise the critical path.  A waveform may be launched during the simulation.

You may also run simulations in the interactive mode:

ocean

At the ocean command, you load the script:

load(“oceanScript.ocn”)

This will allow you to look at the waveforms launched during the simulation.  Type exit to quit ocean.

When the simulation is done, you can see the results in the following file:

            testbench_result.txt

You may also view the waveform of any node by using the results-browser:

icfb > Tools > Analog Environment > Result Browser

     > File > open result > ~/ee115c/cadence-labs/ project/testing/psf/...

Appendix

Filelist in the test_bench.tar

  ./netlist

 ./netlistFooter

 ./netlistHeader

 ./oceanScript.ocn

 ./test_circuitFooter

 ./test_circuitHeader

Last Modified on February 27, 2007 by Dejan Markovic