About
Myself
I am currently a manager
at Mojix, Inc .
From 2005 to 2007, I was a postdoctoral researcher at the
Image
Communications Laboratory ,
UCLA where I worked on synchronization algorithms for deep-space
communications and hardware/software designs for low-power
digital signal processing. In 2004, I completed my PhD in
the Custom Computing Group at the
Department of Computing ,
Imperial College London under
Prof .
Wayne Luk
and
Prof. Peter
Y.K. Cheung .
Areas of Expertise
Circuit optimization, communications, computer arithmetic, design automation, reconfigurable computing (FPGAs), radio-frequency identification (RFID), and signal processing.
Awards
NASA Tech
Brief Award , "Pilotless Frame
Synchronization Using LDPC Code Constraints" , NPO-45032, Awarded Aug 2007, Published Dec 2009.
NASA Tech
Brief Award , "Using LDPC Code Constraints to Aid Recovery of Symbol Timing" ,
NPO-43112, Awarded Jul 2006, Published Oct 2008.NASA-JPL Communications
Systems Research "Featured Accomplishment" , In recognition of
"Hardware-Based Universal LDPC Encoder", Mar 2006.
Full EPSRC PhD
Scholarship , The UK Engineering and Physical Sciences
Research Council, Sep 2001.Runner-up of the Award for
the Best Computer Software Student in the UK , In
recognition of "Compiling High-Level Programs into FPGAs", The UK
Science, Engineering & Technology Student of the Year Awards, Sep 2001.Best First Year Project Prize , In recognition of "Optical
Link Communication using Programmable Logic Devices", Imperial College London,
Jul 1999.
Best Web Korea Award for Top 5 Personal Homepages
in Korea , Kyung-Hyang Il-Bo and Simmani, May 1997.
Publications
1. D. Lee, W. Luk ,
J.D. Villasenor, and P.Y.K. Cheung,
" A Gaussian noise
generator for hardware-based simulations " ,
IEEE Transactions on Computers , volume 53, number 12, pages 1523-1534, Dec 200 4.
2. P.H.W. Leong, G. Zhang, D.
Lee, W. Luk, and J.D. Villasenor,
"A comment on the implementation of the Ziggurat method" ,
Journal of Statistical Software , volume 12, number 7,
Feb 2005.
3. D. Lee, W. Luk, J.D.
Villasenor, G. Zhang, and P.H.W. Leong,
A hardware Gaussian noise generator using the Wallace
method" , IEEE Transactions on VLSI Systems ,
volume 13, number 8, pages 911-920, Aug 2005.
4. D. Lee, A. Abdul Gaffar, O. Mencer,
and W. Luk ,
"Optimizing hardware function evaluation" ,
IEEE Transactions on Computers , volume 54, number 12,
pages 1520-1531, Dec 2005.
5. D. Lee, E.L. Valles, J.D.
Villasenor, and C.R. Jones,
"Joint LDPC decoding and timing recovery using code
constraint feedback" ,
IEEE Communications Letters ,
volume 10, number 3, pages 189-191, Mar 2006.
6. D. Lee, J.D. Villasenor,
W. Luk, and P.H.W. Leong,
"A hardware Gaussian noise generator using the Box-Muller
method and its error analysis" , IEEE Transactions on
Computers , volume 55, number 6, pages 659-671, Jun 2006.
7. D. Lee, A. Abdul Gaffar,
R.C.C. Cheung, O. Mencer, W. Luk, and G.A. Constantinides,
"Accuracy-guaranteed bit-width optimization" ,
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems , volume 25, number 10, pages
1990-2000, Oct 2006.
8.
D. Lee and J .D. Villasenor,
"A bit-width optimization
methodology for polynomial-based function evaluation" ,
IEEE Transactions on
Computers ,
volume 56, number 4, pages 567-571, Apr 2007 .
9.
D. Lee, R.C.C. Cheung, and J .D. Villasenor ,
"A flexible architecture for precise gamma
correction" , IEEE Transactions on VLSI Systems, volume 15, number 4, pages 474-479, Apr 2007.
10.
R.C.C. Cheung, D. Lee, W. Luk ,
and J .D. Villasenor,
"Hardware generation of arbitrary random number
distributions from uniform distributions via the inversion
method" , IEEE Transactions on VLSI Systems, volume 15, number 8, pages 952-962, Aug 2007.
11.
D. Lee, H. Kim, C.R. Jones,
and J.D. Villasenor ,
"Pilotless frame synchronization via LDPC code
constraint feedback" ,
IEEE Communications Letters ,
volume 11, number 8, pages 683-685, Aug 2007.
12.
D. Lee, R.C.C. Cheung, W. Luk,
and J.D. Villasenor ,
"Hardware implementation trade-offs of polynomial approximations and interpolations" ,
IEEE Transactions on Computers ,
volume 57, number 5, pages 686-701, May 2008.
13.
D. Lee, H. Kim, C.R. Jones,
and J.D. Villasenor ,
"Pilotless frame synchronization for LDPC-coded transmission systems" ,
IEEE Transactions on Signal Processing ,
volume 56, number 7, pages 2865-2874, July 2008.
14.
H. Kim, D. Lee,
and J.D. Villasenor ,
"Design tradeoffs and hardware architecture for real-time iterative MIMO detection using sphere decoding and LDPC Coding" ,
IEEE Journal of Selected Areas in Communications ,
volume 26, number 6, pages 1003-1014, August 2008.
15.
H. Kim, M. Rahimi, D. Lee, D. Estrin,
and J.D. Villasenor ,
"Energy-aware high resolution image acquisition via heterogeneous image sensors" ,
IEEE Journal of Selected Topics in Signal Processing ,
volume 2, number 4, pages 526-537, August 2008.
16.
D. Lee
and J.D. Villasenor ,
"Optimized custom precision function evaluation for embedded processors" ,
IEEE Transactions on Computers ,
volume 58, number 1, pages 46-59, January 2009.
17.
D. Lee, R.C.C. Cheung, W. Luk,
and J.D. Villasenor ,
"Hierarchical segmentation for hardware function evaluation" ,
IEEE Transactions on VLSI Systems ,
volume 17, number 1, pages 103-116, January 2009.
18.
D. Lee, H. Kim, M. Rahimi, D. Estrin,
and J.D. Villasenor ,
"Energy-efficient image compression for resource-constrained platforms" ,
IEEE Transactions on Image Processing ,
volume 18, number 9, pages 2100-2113, September 2009.
19.
D. Lee, L. Kim,
and J.D. Villasenor ,
"Precision-aware, self-quantizing hardware architectures for the discrete wavelet transform" ,
IEEE Transactions on Image Processing ,
volume 21, number 2, pages 768-777, February 2012.
- Book Chapters -
1. D. Lee, W. Luk , J. D. Villasenor, and P.Y.K Cheung,
"The effects of polynomial degrees on the hierarchical
segmentation method" , In New Algorithms,
Architectures, and Applications for Reconfigurable Computing ,
chapter 24, W. Rosenstiel and P. Lysaght (Eds.), Springer-Verlag,
Dec 2004.
- Conference Papers -
1. D. Lee, T.K. Lee, W. Luk, and P.Y.K. Cheung,
"Incremental programming for reconfigurable engines" , In Proc. IEEE
International Conference on Field-Programmable Technology
(FPT) , pages 411-415, Shatin, Hong Kong, Dec 2002.
2. D. Lee, W. Luk, J .D. Villasenor, and
P.Y.K. Cheung,
"A hardware Gaussian noise generator for channel code
evaluation" , In Proc. IEEE
Symposium on Field-Programmable Custom Computing Machines (FCCM) , pages 69-78,
Napa Valley, USA, Apr 2003.
3. D. Lee, W. Luk, J .D. Villasenor, and P.Y.K. Cheung,
"Non-uniform segmentation for hardware function evaluation" , In Proc.
International Conference on Field Programmable Logic and its
Applications (FPL) , pages 796-807, LNCS 2778, Springer-Verlag, Lisbon, Portugal, Sep 2003.
4. D. Lee, W. Luk , J .D. Villasenor, and P.Y.K. Cheung,
" Hierarchical segmentation schemes for function
evaluation " , In
Proc. I EEE International Conference on
Field-Programmable Technology
(FPT) , pages 92-99, Tokyo, Japan, Dec 200 3 .
5. D. Lee, W. Luk , C. Wang, C.R. Jones, M. Smith, and J .D. Villasenor ,
" A flexible hardware encoder for low-density
parity-check codes " , In Proc. I EEE Symposium on Field-Programmable Custom
Computing Machines
(FCCM),
pages 101-111, Napa Valley, USA, Apr 200 4.
6. D. Lee,
O. Mencer, D.J. Pearce, and W. Luk ,
"Automating optimized
t able-with- p olynomial
f unction
e valuation for FPGAs" , In Proc. International Conference on Field Programmable
Logic and its Applications (FPL) , pages 364-373, LNCS 3203, Springer-Verlag, Antwerp, Belgium, Aug 200 4 .
7. D. Lee,
" Gaussian
noise generation for Monte Carlo
simulations in hardware " , In Proc.
The Korean Scientists
and Engineers Association in the UK (KSEAUK) 30th
Anniversary
Conference , pages 182-185, London, UK, Sep 200 4 .
8. D. Lee,
A. Abdul Gaffar , O. Mencer, and W. Luk,
"Adaptive
r ange
r eduction for
h ardware
f unction
e valuation" , In Proc.
I EEE International Conference on
Field-Programmable Technology (FPT) , pages 169-176 , Brisbane, Australia, Dec 200 4 .
9. D. Lee,
A. Abdul Gaffar , O. Mencer, and W. Luk ,
" MiniBit: bit-width optimization via affine
arithmetic " , In Proc. ACM/IEEE Design Automation Conference (DAC) , pages 837-840,
Anaheim, USA, Jun 200 5.
10.
G. Zhang, P.H.W. Leong, D. Lee, J .D. Villasenor , R.C.C. Cheung, and W. Luk ,
" Ziggurat-based hardware Gaussian random number
generator " , In Proc. IEEE International Conference on Field Programmable
Logic and its Applications (FPL) , Tampere, Finland, Sep 200 5 .
11. R.C.C. Cheung, D. Lee, O. Mencer, W. Luk, and
P.Y.K. Cheung,
"Automating custom-precision function evaluation for
embedded processors" , In Proc. ACM/IEEE International Conference
on Compilers, Architecture, and Synthesis for Embedded
Systems (CASES) , pages 22-31, San Francisco, USA, Sep 2005.
12. G. Zhang, P.H.W. Leong,
C.H. Ho, K.H. Tsoi, C.C.C. Cheung, D. Lee, R.C.C. Cheung, and
W. Luk,
"Reconfigurable acceleration for Monte Carlo based financial
simulation" , In Proc.
I EEE International Conference on
Field-Programmable Technology
(FPT) ,
Singapore, Dec 2005.
13. D. Lee, R.C.C. Cheung,
J.D. Villasenor, and W. Luk,
"Inversion-based hardware Gaussian random number generator:
a case study of function evaluation via hierarchical
segmentation" , In
Proc. I EEE International Conference on Field-Programmable
Technology (FPT) , pages 33-40, Bangkok, Thailand, Dec 2006.
14. D. Lee, H. Kim, S. Tu, M.
Rahimi, D. Estrin, and J.D. Villasenor,
"Energy-optimized image communication on
resource-constrained sensor platforms" , In Proc.
I EEE/ACM International Conference on Information
Processing in Sensor Networks: Special Track on Sensor
Platforms, Tools and Design Methods (SPOTS) , pages 216-225, Cambridge, USA, Apr 2007.
- Theses / Reports -
1.
D. Lee ,
" Hardware
compilation and resource sharing optimisations " , BEng Final Year Project Report ,
Imperial College London,
Jun 200 1.
2.
D. Lee ,
"Reconfigurable
hardware for function evaluation and LDPC coding " , MPhil/PhD Transfer Report ,
Imperial College London,
Jul 200 3 .
3.
D. Lee,
" Hardware designs for function evaluation and LDPC
coding " , PhD Thesis , Imperial College
London,
Oct 200 4.
Professional Activities Program Committee Member, IEEE International Conference on Field
Programmable Logic and its Applications Reviewer of IEEE Transactions on Computers, IEEE Transactions on VLSI Systems, IEEE Transactions on Communications, FCCM,
FPGA, FPL, FPT, and Globecom.
Contact Details
Email:
donglee79@gmail.com
Last
update: January 17, 2012
Visits since May 26, 2003:
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Professional Activities 