Zhe Feng's homepage

$说明: C:\Documents and Settings\optimist81\Desktop\myphoto-small.jpg$

Zhe (Frank) Feng 冯哲

Ph.D. Candidate

53-109, Engineering IV, Los Angeles, CA 90095
feng07 at ucla dot edu [linkedin]

[WORK EXPERIENCE] [RECENT PUBLICATIONS] [NEWS] [RESUME] [LINKS]

Zhe Feng received his B.S. and M.S. in 2004 and 2007 respectively from Department of Computer Science in Northeastern University and Tsinghua University in China. In August 2007, he moved to Los Angeles from China to pursue his Ph.D. degree in Electrical Engineering, UCLA, and jointed the Design Automation Laboratory led by Prof. Lei He. Two months later, his lovely wife, Ann Han jointed with him.

RESEARCH INTERESTS

Solving large scale, highly complex technical problems
Computer-Aided Design algorithms for VLSIs
High level synthesis/ESL design methodology
Logic synthesis algorithms
Placement and routing algorithms

WORK EXPERIENCE

2007-present Electrical Engineering, UCLA

Graduate Student Researcher, participating research projects on FPGA synthesis for power reduction and soft errors mitigation.

06/2011-09/2011 Altera Inc. , San Jose

Intern, software development for Exclusive-OR optimization based on intersection algorithm for Quartus software suite.

06/2010-09/2010 AutoESL Design Technologies (Xilinx Inc.), Los Angeles

Intern, software development for synthesis performance prediction by fast compilation based on LLVM and Berkeley ABC.

06/2008-09/2008 Synopsys Inc., Sunnyvale, CA

Intern, software development for power experimental system and RTL power estimation for Synopsys low power flow.

2004-2007 Computer Science Dept., Tsinghua University, Beijing, China

Graduate Research Assistant, participating in fundamental research for VLSI CAD, especially on placement and routing.

06/2006-09/2006 HT-EDA Corp. (ICScape Inc.), Beijing, P.R.China

Intern, software development for Engineering Change Order (ECO) router.

RECENT PUBLICATIONS

Zhe Feng, Naifeng Jing, Yu Hu, and Lei He, IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-based FPGAs, FPL 2011
Naifeng Jing, Ju-Yueh Lee, Zhe Feng et al., Quantitative SEU Fault Analysis for SRAM-Based FPGA Architectures and Synthesis Algorithms, FPL 2011.
Zhe Feng and Lei He, Logic Synthesis for Soft Error Resilience in FPGAs, Ph.D. Forum at DAC 2011.
Ju-Yueh Lee, Zhe Feng and Lei He, In-Place Decomposition for Robustness in FPGA, ICCAD 2010.
Zhe Feng, Yu Hu, Lei He and Rupak Majumdar, IPR: In-Place Reconfiguration for FPGA Fault Tolerance, ICCAD 2009. (Best Paper Award nomination)
Yu Hu, Zhe Feng, Lei He, and Ruapk Majumdar, Robust FPGA Resynthesis Based on Fault Tolerant Boolean Matching, ICCAD 2008. (Best Paper Award nomination)
More

NEWS

My two papers were accepted by International Conference on Field Programmable Logic and Applications (FPL) 2011. (May 25th, 2011)
My submission was accepted by Ph.D. Forum at DAC, 2011, and to be presented on June 7th in San Diego. (May 2nd, 2011)
Invited talk on fault-tolerance techniques for FPGA in Altera Inc. (June, 2011)
Started my internship in Altera Inc. (June, 2011)
Invited talk in AutoESL Design Technologies (Xilinx Inc.). (Sep, 2010)
Started my internship in AutoESL Design Technologies, (acquired by Xilinx Inc.). (June 21th, 2010)
Invited as Technical Program Committee Member for International Conference on Field-Programmable Technology (FPT) 2011. (June, 2010)
Presented my paper at ICCAD 2009 in San Jose (Nov. 2th, 2009).
My paper IPR: In-Place Reconfiguration for FPGA Fault Tolerance was nominated to IEEE/ACM William J. McCalla ICCAD Best Paper Award 2009. (Sep. 14th, 2009)
Passed Ph.D. qualifying exam and was advanced to a Ph.D. Candidate. (August. 25th, 2009)
Received UCLA Chancellor's Prize. (April. 28th, 2009)
Ann was admitted by EECS Dept. in UCI and got her F1 visa. Our home moved to Irvine, Orange County. (Jan. 5th, 2009)
My paper Robust FPGA Resynthesis Based on Fault Tolerant Boolean Matching was nominated to IEEE/ACM William J. McCalla ICCAD Best Paper Award 2008. (Jul. 8th, 2008)
Invited talk in Synposys Inc. (Sep, 2008)
Moved to San Jose for my summer internship in Synopsys Inc. (Jun. 15th, 2008)
Received UCLA Chancellor's Prize. (May. 6th, 2008)
Passed Ph.D. prelim. (April. 16th, 2008)
Received UCLA Electrical Engineering Department Fellowship in Fall 2007. (Aug. 22th, 2007)

Created: 10/18/2006, Updated: 10/18/2011