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J1. Tong Jing, Yu Hu, Zhe Feng, Xian-Long
Hong, Xiaodong Hu, Guiying Yan A
Full-scale Solution to the Rectilinear Obstacle-Avoiding Steiner Problem,
Elsevier INTEGRATION, the VLSI Journal, 2008, 41(3): pp. 413-425.
J2. Zhen Cao, Tom Tong Jing, Jinjun
Xiong, Yu Hu, Zhe Feng, Lei He, Xian-Long Hong Fashion: A Fast and Accurate Solution to Global
Routing Problem, IEEE Trans. on COMPUTER-AIDED DESIGN of Integrated
Circuits and Systems (TCAD), 2008, 27(4): pp.726-737.
J3. Tong Jing, Zhe Feng, Yu Hu,
Xianlong Hong, Xiaodong Hu, Guiying Yan, λ-OAT:
λ-Geometry Obstacle-Avoiding Tree Construction with O(nlogn) Complexity,
IEEE Trans. on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD),
2007, 26(11): pp.2073-2079.
J4. Yu Hu, Tong Jing, Zhe Feng,
Xianlong Hong, Xiaodong Hu, Guiying Yan, ACO-Steiner:
Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm,
Journal of Computer Science and Technology (JCST), 2006, 21(1): pp.147-152.
J5. Yu Hu, Zhe Feng, Tong Jing,
Xianlong Hong, Yang Yang, Ge Yu, Xiaodong Hu, Guiying Yan, FORst: A 3-Step Heuristic for Obstacle-Avoiding
Rectilinear Steiner Minimal Tree Construction, Journal of Information &
Computational Science, 2004, 1(3): pp.107-116.
C1. Zhe
Feng, Naifeng Jing, Yu Hu, and Lei He, IPF:
In-Place X-Filling to Mitigate Soft Errors in SRAM-based FPGAs, FPL 2011
C2. Naifeng Jing, Ju-Yueh Lee, Zhe Feng et al., Quantitative SEU Fault
Analysis for SRAM-Based FPGA Architectures and Synthesis Algorithms, FPL 2011.
C3. Ju-Yueh Lee, Zhe Feng and Lei He, In-Place
Decomposition for Robustness in FPGA, ICCAD, 2010.
C4. Zhe Feng, Yu Hu, Lei He and
Rupak Majumdar, IPR: In-Place Reconfiguration for FPGA Fault
Tolerance, ICCAD 2009.(Best Paper Award nomination)
C5. Yu Hu, Zhe Feng, Lei He, and
Ruapk Majumdar, Robust FPGA Resynthesis Based
on Fault Tolerant Boolean Matching, ICCAD
2008. (Best Paper Award
nomination)
C6. Zhe Feng, Yu Hu, Tong Jing,
Xianlong Hong, Xiaodong Hu, Guiying Yan, An
O(nlogn) Algorithm for Obstacle-Avoiding Routing Tree
Construction in the λ-Geometry Plane, ISPD, 2006.
C7. Yiyu Shi, Tong Jing, Lei He, Zhe
Feng, Xianlong Hong, CDCTree: Novel
Obstacle-Avoiding Routing Tree Construction Based on Current Driven Circuit
Model, ASP-DAC, 2006.
C8. Yu Hu, Tong Jing, Xianlong Hong, Zhe
Feng, Xiaodong Hu, Guiying Yan, An-OARSMan:
Obstacle-Avoiding Routing Tree Construction with Good Length Performance,
ASP-DAC, 2005.
C9. Yu Hu, Zhe Feng, Tong Jing,
Xianlong Hong, Yang Yang, Ge Yu, Xiaodong Hu, Guiying Yan, A 3-Step Heuristic for Obstacle-Avoiding
Rectilinear Steiner Minimal Tree Construction, ISC&I, 2004.
C10. Yu Hu, Tong Jing, Xianlong Hong, Zhe
Feng, Xiaodong Hu, Guiying Yan, An
Efficient Rectilinear Steiner Minimum Tree Algorithm Based on Ant Colony
Optimization, ICCCAS, 2004.
W1. Zhe
Feng and Lei He, Logic Synthesis for Soft Error Resilience in FPGAs, Ph.D.
Forum at DAC, 2011.
W2. Zhe
Feng, Yu Hu, Rupak Majumdar and Lei He, IPR: InPlace Reconfiguration for
FPGA Fault Tolerance, International Workshop on Logic and Synthesis, 2009.
W3. Yu Hu, Zhe Feng, Rupak Majumdar and Lei He, Templates and Algorithms of
Boolean Matching for Fault Tolerance in FPGAs, International Workshop on Logic
and Synthesis, 2008.
P1. A method for obstacle-avoiding
routing tree construction with good wire-length performance. (Chinese patent 200410090885.5.
published on 2005/04/06), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng,
and Yang Yang.
P2. A method for obstacle-avoiding
rectilinear Steiner minimum tree construction. (Chinese patent 200410069118.6,
published on 2005/03/02), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng,
and Yang Yang.
Created: 10/18/2006,
Updated: 10/18/2011