Alireza Razzaghi was born in Tehran, Iran. He received his B.Sc. from Iran
University of Science and Technology and his M.Sc. from Tehran University
both in Electrical Engineering. During his Master's program, he focused on
designing on-chip signal processing circuitry for implantable multielectrod
arrays collecting neuro biopotentials. As his Master's project, he designed
a low-noise low-offset instrumentation amplifier for the front-end of the
implantable multielectrode probes.
Alireza is completing his Ph.D. under the supervision of Professor Frank
Chang in the High Speed Electronics Laoratory (HSEL) of the Electrical
Engineering Department at UCLA. His main research was a 10b 1GS/s pipelined
cascaded folding ADC in a 0.35um SiGe BiCMOS process for Digital Radar
Receivers. He managed a team of five students to conduct this project.
Alireza has designed a 6b 1GS/s ADC in a 0.25um CMOS process and a 10b 1GS/s track-and-hold amplifer in a 0.5um SiGe BiCMOS process. His research
interests are mixed-signal design with emphasis on analog-to-digital and
He is an IEEE student memeber.
Razzaghi, A., Chang, M.F., "A 10-b, 1-GSample/s track-and-hold amplifier
using SiGe BiCMOS technology" Proceedings of the Custom Integrated Circuits
Conference (CICC), 433-436 (September 2003) San Jose, CA.