Email: gsbyun@ee.ucla.edu       Gyung-Su Byun received the Ph.D. degree in electrical engineering from the UCLA, Los Angeles, in 2010. Since 2011, he is currently an Assistant Professor in the Lane Department of Electrical Engineering, West Virginia University, Morgantown, West Virginia. From 1999 to 2005, he was a Senior Design Engineer with Samsung Electronics, where he worked on the design of low power and high speed DRAMs such as DDR2, GDDR3, Rambus and XDR. In 2006, he was a research intern with Intel Corporation where he worked on the design of a cache memory and a 3D chip multi-processor (CMP) with RISC core architecture. From 2007 to 2011, he was a Senior Design Engineer with Inphi Corporation, where he worked on the design of a DLL/PLL, high-speed I/O interface and advanced memory buffers. His research interests are low-power digital electronics, mixed-signal integrated circuit and system design, high speed CMOS interconnect for wire-line and wireless communication and energy-efficient memory and multi-core architecture. He is the author/co-author of over 12 papers and holds 20 patents in the field of electronic circuits. [Key publications] - IEEE ISSCC 2011, G.-S. Byun et al.,"An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using SBD Dual (Base+RF) band signaling" - IEEE Journal of Solid State Circuit (JSSC), G.-S. Byun et al, "An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using SBD Dual (Base+RF)-Band Signaling" - IEEE International Conference on Computer Design (ICCD 2011), "The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System"