Email: qung@ee.ucla.edu       Qun Jane Gu received the B.S. and M.S. from Huazhong University of Science and Technology, Wuhan, China, in 1997 and 2000, the M.S. from the University of Iowa, Iowa City, in 2002 and the Ph.D. from University of California, Los Angeles in 2007 all in electrical engineering. She received UCLA fellowship in 2003 and Dissertation Year Fellowship in 2007. After that, she joined Wionics Realtek research group as a senior design engineer on CMOS 60GHz transceiver for System-on-Chip. Since March 2009, she is a postdoctoral researcher in UCLA.       She and her colleagues demonstrated record energy efficiency (0.39pJ/bit and 0.27pJ/bit respectively) interconnect systems for 3D IC technology and for intra/inter chip communications. They also implemented a 450GHz CMOS VCO with fundamental frequency (225GHz) higher that device fT, as well as a fastest frequency and widest locking range CMOS frequency divider with 162GHz~192GHz dividing range and 2.4mW power consumption. Research interests high efficiency, low power interconnect, mm-wave and sub-mm-wave integrated circuits and SoC techniques, as well as CMOS THz systems. Publications "A Low Power V-band CMOS Frequency Divider with Wide Locking Range and Accurate Quadrature Output Phases", Q. Gu, Z. Xu, D. Huang, T. LaRocca, N.-Y. Wang W. Hant and M.-C. F. Chang, submitted to JSSC "A Wide Locking Range and Low Power V-band Frequency Divider in 90nm CMOS", Q. Gu, Z. Xu and M.F. Chang, 2007 Symposium on VLSI Technology and Circuits, pp 166-167 "Two 10 Gb/s/pin Low Power Interconnect Methods for Three-Dimensional Integrated Circuits", Q. Gu, Z. Xu, J. Ko and M.F. Chang, IEEE ISSCC 2007 Dig. Tech. Papers , pp 448-449 "A 60GHz CMOS Differential Receiver Front-End Using On-Chip Transformer for 1.2 Volt Operation with Enhanced Gain and Linearity", D. Huang, R. Wong, Q. Gu, N. Wang, T. Ku, C. Chien and M.F. Chang, 2006 Symposium on VLSI Technology and Circuits, pp. 144-145 "A 60GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric for Size, Loss and Noise Reduction", D. Huang, W. Hant, N-Y, Wang, T. Ku, Q. Gu, R. Wong, F. Chang, IEEE ISSCC 2006 Dig. Tech. Papers, pp. 314-315 "Advanced RF/Baseband Interconnect Schemes for Inter- and Intra-ULSI Communications", M. F. Chang, I Verbauwhede, C. Chien, Z. Xu, J. Kim, J. Ko, Q. Gu and B.Lai, 2005 IEEE Trans. On Electron Devices, pp.1271-1285 "A Compact Dual-band Direct-Conversion CMOS Transceiver for 802.11 a/b/g WLAN", Z. Xu, S. Jiang, Y. Wu, H. Jian, G. Chu, K. Ku, P. Wang, N. Tran, Q. Gu, M. Lai, C. Chien, M. F. Chang, R. D. Chow, IEEE ISSCC 2005 Dig. Tech. Papers, pp. 98-99 "An RF/Baseband FDMA-Interconnect Transceiver for Reconfigurable Multiple Access Chip-to-Chip Communication", J. Ko, J. Kim, Z. Xu, Q. Gu, C. Chien and M. F. Chang, IEEE ISSCC 2005 Dig. Tech. Papers, pp. 338-339 "Method and Apparatus for Frequency Detecting and Locking in Costas Loop", J. Ko, Q. Gu, Z. Xu and M. F. Chang, patent submitted "Self-Synchronized RF Interconnect for 3-Dimensional Circuit Integration", Q. Gu, Z. Xu, J. Ko and M. F. Chang, Patent publication NO. 20060256964 "Three-Dimensional Circuit Integration Based on Self-Synchronized RF-Interconnect using Capacitive Coupling", Q. Gu, Z. Xu, J. Kim, J. Ko and M. F. Chang, 2004 Symposium on VLSI Technology and Circuits, pp. 96-97 "A Self-Synchronized RF-Interconnect For 3-Dimensional Integrated Circuits", Q. Gu, Z. Xu, J. Ko, S. Hsien and M. F. Chang, IEEE International Symposium Circuits and Systems (ISCAS 2004), pp. 317-320