Yen-Hsiang Wang was born in Taipei city, Taiwan. He received the B.S. degree in Electrical Engineering from National Taiwan University (NTU) in 2008. The bachelor project was a 24GHz power amplifier with 10dBm P1dB in 0.18um CMOS. Later on he obtained the M.S. degree from University of California, Los Angeles (UCLA) in 2011. The master thesis was on a low-power ADC design for 60GHz wireless communication. He is currently pursuing the Ph.D. degree at UCLA. In 2007 he worked as an internship in Wireless Communication group in MediaTek Inc.
Ku, I.; Xu, Z.; Kuan, Y.C.; Wang, Y.H.; Chang, M.-C.F.;, “A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging ADC for Low-Power Gigabit Wireless Communications in 65-nm CMOS,” Custom Integrated Circuits Conference, 2011
CMOS high-speed mixed-signal circuit design, CMOS RF circuit design