The High Speed Electronics Laboratory is currrently working on the projects as highlighted below. Advanced Interconnects and I/O Realized world's 1st CDMA-interconnect based on code-division multiple access for simultaneous multiple-I/O (2x2) inter-chip communication at a data rate of 2.7Gbps Realized world's 1st FDMA-interconnect for simultaneous multiple-I/O and bidierectional inter-ULSI bus and link with a RF/baseband combined data rate of 3.6Gbps Developed world's 1st capacitor-coupled pulsed signaling bus interface (CCBI) for Gbps ultra low power board-level communication Demonstrated self-synchronized RF-interconnect for 3-Dimensional ICs CMOS MMICs Realized world's 1st K-band receiver front-end at 24GHz in 0.18 m CMOS Realized low phase noise CMOS VCOs (F.O.M. of -187dBc/Hz) at 60 and 70GHz, respectively, with small on-chip tuning folk (X36 reduction in size) on high dielectric constant photonic crystal Realized 60GHz differential CMOS LNA with 20dB gain, 5dB NF, 2GHz 3dB bandwidth and 5mW power consumption High Speed ADCs/DACs Realized a 2Gs/s 3-bit Sigma Delta-modulated DAC in InP HBTs with 72dB SNR Realized a 2Gs/s 6-bit Nyquist ADC in 0.18 m CMOS with 1GHz instantaneous bandwidth and SNDR/SFDR of 30 and 35.5dB, respectively Realized a 600Ms/s 8-bit Nyquist ADC in 0.18 m CMOS with minimum SNDR of 40dB at 600Msample/s for input signals up to 200MHz