Home > Publications

Publications (sorted by topics, types, years)

| FPGA | Wireless Healthcare | RSMT | VLSI Routing | Interconnect | Testing |

Design, Architecture and Synthesis for FPGAs

  1. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, and Minming Li, Fault-Tolerant Resynthesis for Dual-Output LUTs, ASP-DAC, 2010, (the preliminary version was presented in SELSE, 2009).
  2. Lei He and Yu Hu, Power-Efficient and Fault-Tolerant Circuits and Systems, ASICON, 2009. (Invited paper)
  3. Zhe Feng, Yu Hu, Rupak Majumdar and Lei He, IPR: InPlace Reconfiguration for FPGA Fault Tolerance, ICCAD, 2009, (the preliminary version was presented in IWLS, 2009).
  4. Wenyao Xu, Jia Wang, Yu Hu and Lei He, Retiming for Single Event Transient Mitigation in FPGAs, IWLS, 2009.
  5. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, Design and Synthesis of Programmable Logic Block with Mixed LUT and Macro-Gate, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2009.
  6. Yu Hu, Zhe Feng, Rupak Majumdar, and Lei He, Robust FPGA Resynthesis Based on Fault Tolerant Boolean Matching, ICCAD, 2008, (Best paper award nomination). (The preliminary verson, Templates and Algorithms of Boolean Matching for Fault Tolerance in FPGAs, was presented in IWLS, 2008).
  7. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetries to Speed-Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2008.
  8. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, Mapping and Resynthesis for LUT-based FPGAs with an Efficient SAT-Based Boolean Matching, IWLS, 2008 (Best Contribution Award of the IEEE Programming Contest at IWLS 08).
  9. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis. DAC, 2008, (the preliminary version was presented in IWLS, 2008).
  10. Yu Hu, Yan Lin, Lei He and Tim Tuan, Pysical Synthesis for FPGA nterconnect Power Reduction bby Dual-Vdd udggeting and Retiming, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2008.
  11. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping. ICCAD, 2007 (the preliminary version was presented in IWLS, 2007).
  12. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates. ICCAD, 2007 (the preliminary presented in IWLS, 2007).
  13. Yu Hu, Yan Lin and Lei He, Retiming for High Performance FPGAs Considering Flipflop Constraints and Process Variations. Poster in ISFPGA, 2007.
  14. Yan Lin, Yu Hu, Lei He, and Vijay Raghunat. An Efficient Chiplevel Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction. ISLPED, 2006, pp. 168-173.
  15. Yu Hu, Yan Lin, Lei He and Tim Tuan. Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction. DAC, 2006, pp. 478-483.

Wireless Healthcare

  1. Yu Hu, Yi-Tao Wang, Adam Stoelting, Yi Zou and Majid Sarrafzadeh, Smart Cushion: A Case Study on Wireless Healthcare Application Development, IEEE Potentials Magazine, 2009.

Heuristics for Rectilinear Steiner Tree Construction

  1. Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu and Guiying Yan, A full scale solution to the rectilinear obstacle-avoiding Steiner problem, Integration, the VLSI Journal, 2007.
  2. Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu and Guiying Yan, Lambda-OAT: Lambda-Geometry Obstacle-Avoiding Tree Construction with O(nlogn) Complexity. IEEE Transaction on Computer-Aided Design of Circuits and Systems, 26(11), 2007, pp 2073-2079.
  3. Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu and Guiying Yan. An O(nlogn) Algorithm for Obstacle-Avoiding Routing Tree Construction in the λ-Geometry Plane. ISPD, 2006, pp. 48-55. 
  4. Yu Hu, Tong Jing, Xian-Long Hong, Zhe Feng, Xiao-Dong Hu, and Gui-Ying Yan, ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm, Journal of Computer Science & Technology, 2006, 21(1), pp. 147-152.
  5. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan. An-OARSMan: Obstacle-Avoiding Routing Tree Construction with Good Length Performance. ASP-DAC, 2005, pp. 7-12.
  6. Yu Hu, Zhe Feng, Tong Jing, Xianlong Hong, Yang Yang, Ge Yu, Xiaodong Hu, Guiying Yan. A 3-Step Heuristic for Obstacle-Avoiding Rectilinear Steiner Minimum Tree Construction. ISC'I 2004, pp.1017-1021.
  7. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan. An Efficient Rectilinear Steiner Minimum Tree Algorithm Based on Ant Colony Optimization. ICCCAS 2004, pp. 1276-1280.
  8. Yu Hu, Zhe Feng, Tong Jing, Xianlong Hong, Yang Yang, Ge Yu, Xiaodong Hu, and Guiying Yan. FORst: A 3-Step Heuristic for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. Journal of Information & Computational Science, 2004, 1(3), pp: 107-116.
  9. A method for obstacle-avoiding routing tree construction with good wire-length performance. (Chinese patent 200410090885.5. published on 2005/04/06), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng, and Yang Yang.
  10. A method for obstacle-avoiding rectilinear Steiner minimum tree construction. (Chinese patent 200410069118.6, published on 2005/03/02), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng, and Yang Yang.

Global Routing

  1. Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, and Xianlong Hong, Fashion: A Fast and Accurate Solution to Global Routing Problem, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2008.
  2. Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, and Xianlong Hong. DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC, 2007, pp. 256 - 261.
  3. Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, and Guiying Yan. DraXRouter: Global Routing in X-Architecture with Dynamic Resource Assignment. ASP-DAC 2006, pp. 618-623.
  4. Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, and Guiying Yan. A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS V 2005, LNCS 3553, pp. 344-353.
  5. YangYang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu and Guiying Yan. Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP 2005, pp 198-203.
  6. Yu Hu, Tong Jing, Xianlong Hong, Qiang Zhou, and Ming Shen, VLSI Layout System Integration Based on Multi-Layer Mechanism, Journal of Computer-Aided Design & Computer Graphics, 2005(17). (In Chinese)
  7. Yu Hu, Tong Jing, Xianlong Hong, Qiang Zhou, Ming Shen. A Practical and Efficient Integrated System for VLSI/ULSI Physical Design. ICCCAS 2004, pp. 1233-1237.
  8. Yu Hu, Tong Jing, Xianlong Hong, Qiang Zhou, and Ming Shen, Data Management for Data-Path Layout System, Journal of Microelectronics, 33(4), pp.301-305, Aug. 2003. (In Chinese)
  9. A method for timing-driven global routing considering coupling effects. (Chinese patent 03124095.X, published on 2004/02/04) By Xianlong Hong, Tong Jing, Jingyu Xu, Ling Zhang, and Yu Hu.
  10. A method for standard cell global routing considering crosstalk reduction. (Chinese patent 02156622.4, published on 2003/05/07) By Xianlong Hong, Tong Jing, Jingyu Xu, Ling Zhang, and Yu Hu.

Interconnect Optimization

  1. Hao Yu, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Synthesis Considering Time Variant Temperature Gradient. SRC Techcon Conference, 2007.
  2. Hao Yu, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Embedding Considering Time Variant Temperature Gradient. ISPD, 2007, pp. 173 - 180.
  3. King Ho Tam, Yu Hu, Lei He, Tong Jing and Xinyi Zhang, Dual Vdd Buffer Inser tion for Power Reduction, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2008.
  4. Yu Hu, King Ho Tam, Tong Jing and Lei He, Fast Dual-Vdd Buffering Based on Interconnect Prediction and Sampling. SLIP,2007, pp. 95 - 102.

Testing

  1. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, and Lei He, Simultaneous Test Pattern Compaction, Ordering and X-Filling for Testing Power Reduction , ISQED, 2009.

 

Created: 2005,