Hao Yu
Ph. D 2006
Department of Electrical Engineering
University of California at Los Angeles
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Hao YuPh. D 2006Department of Electrical Engineering
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Engineering Building IV 53-135W Los Angeles, CA 90095 Tel: (310) 902-7847 email: hy255 at ee dot ucla dot edu
I obtained my B.S. from Fudan University (Shanghai, China) in 1999, and have graduated from UCLA with M.S. and Ph. D in 2007. I was with Berkeley Design Automation for developing the fastest analog/RF SPICE (EDN-Innovation-Award and Red-herring-100) since 2007, and I am now with Nanyang Technological University (Singapore). Please contact haoyu at ntu dot edu dot sg for further information such as Ph.D/Postdoc fellowship support. My new homepage is here. |
| J1. | Hao Yu, and Lei He, "A Provably Passive and Cost Efficient Model for Inductive Interconnects", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), August 2005. (pdf) |
| J2. | Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, and Lei He, "Wideband Passive Multi-Port Model Order Reduction and Realization of RLCM Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), August 2006. (pdf) |
| J3. | Yiyu Shi, Paul Mesa, Hao Yu, and Lei He, "Circuit Simulated Obstacle-Aware Steiner Routing", ACM Transactions on Design Automation of Electronic Systems (TODAES), August 2007. (pdf) |
| J4. | Hao Yu, Yiyu Shi, Lei He, and Tanay Karnik, "3D IC Design Considering Spatially and Temporally Variant Thermal Power", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), December 2008. (pdf) |
| J5. | Hao Yu, Joanna Ho and Lei He, "Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity" ACM Transactions on Design Automation of Electronic Systems (TODAES), May 2009. (pdf) |
| J6. | Hao Yu, Lei He, and M.C.Frank Chang, "Robust On-chip Signaling using Staggered and Twisted Interconnect", IEEE Design and Test of Computers (DTC), September 2009 (SRC inventor award 2008). (pdf) |
| J7. | Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He and Sheldon X.D. Tan, "Fast Analysis of Large Scale Inductive Interconnect by Block Structure Preserved Macromodeling", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2009 (in press) (pdf) |
| C1. | Hao Yu, and Lei He, "Vector Potential Equivalent Circuit Based on PEEC Inversion", ACM/IEEE Design Automation Conference (DAC), June 2003. (pdf) |
| C2. | Hao Yu, Lei He, Zhenyu Qi, and Sheldon X.-D. Tan, "A Wideband Realizable Circuit-Reduction for RLCM Interconnects", IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2005. (pdf) |
| C3. | Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, and Lei He, "Wideband Modeling of RF/Analog Circuits via Hierarchical Multi-Point Model Order Reduction", IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2005. (pdf) |
| C4. | Hao Yu, and Lei He, "Analysis and Synthesis of Staggered Twisted Bundle for Crosstalk Reduction", IEEE/ACM International Symposium on Quality Electronic Design (ISQED), March 2005. (ps) |
| C5. | Hao Yu, and Lei He, "VPEC Sparsification by Generalized Schur's Interpolation", IEEE International Symposium on Circuits and Systems (ISCAS), May 2005. (pdf) |
| C6. | Hao Yu, Lei He, and Sheldon X.-D. Tan, "BSMOR: Block Structure Preserving Model Order Reduction", IEEE International Behavioral Modeling and Simulation Conference (BMAS), September 2005. (pdf) |
| C7. | Yiyu Shi, Hao Yu, and Lei He, "SAMSON: Generalized Second-Order Arnoldi Method for Model Order Reduction with Multiple Non-impulse Sources", ACM International Symposium on Physical Design (ISPD), April 2006. (pdf) |
| C8. | Hao Yu, Yiyu Shi, and Lei He, "TBS: Fast Analysis of Structured Power Grid by Triangularization Based Structure Preserving Model Order Reduction", ACM/IEEE Design Automation Conference (DAC) (Best Paper Award Nomination) , July 2006. (package is released in 09/2006) (pdf)(ppt) |
| C9. | Yiyu Shi, Paul Mesa, Hao Yu, and Lei He, "Circuit Simulation Based Obstacle-aware Steiner Routing", ACM/IEEE Design Automation Conference (DAC), July 2006. (pdf) |
| C10. | Hao Yu, Yiyu Shi, Lei He, and Tanay Karnik "Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power", ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), October 2006. (pdf) |
| C11. | Hao Yu, Joanna Ho, and Lei He, "Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs", IEEE/ACM International Conference of Computer-Aided-Design (ICCAD) (Best Paper Award Nomination) , November 2006. (pdf)(ppt) |
| C12. | Hao Yu, Yiyu Shi, Lei He and David Smart, "BVOR:A Localized Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits", IEEE/ACM International Conference of Computer-Aided-Design (ICCAD), November 2006. (pdf)(ppt) |
| C13. | Hao Yu, Yu Hu, Chuenchen Liu, and Lei He, "Minimal Skew Clock Embedding Considering Time Variant Temperature Variation with Automatic Correlation Extraction", ACM International Symposium on Physical Design (ISPD), March 2007. (pdf) |
| C14. | Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, and Hao Yu, "General block structure-preserving reduced order modeling of interconnect circuits", IEEE/ACM International Symposium. on Quality Electronic Design (ISQED), March 2007. (pdf) |
| C15. | Hao Yu, Chunta Chu, and Lei He, "TBS2: System-in-Package Decoupling Capacitor Allocation for Chip Package Co-Design", ACM/IEEE Design Automation Conference (DAC), July 2007. (pdf) |
| C16. | Hai Wang, Hao Yu, and Sheldon X.D. Tan, "Fast Clock Skew Analysis Considering Environmental Uncertainty by Parameterized and Incremental Macro-models", IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2009. (pdf) |
| C17. | Fang Gong, Hao Yu, and Lei He, "Picap: a parallel and incremental full-chip capacitance extraction considering random process variation ", ACM/IEEE Design Automation Conference (DAC), July 2009. (pdf) |
| C18. | Hao Yu, Xuexin Liu, Hai Wang and Sheldon X.D. Tan, "A Fast Analog Mismatch Analysis by an Incremental and Stochastic Trajectory Piecewise Linear Macromodel", IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2010 (to appear). |
| P1. | Hao Yu, "Structured and Parameterized Macromodeling for High Performance Mixed-mode System Integration", Ph.D. Forum at ACM/IEEE Design Automation Conference, July 2006, Defense Talk at UCLA, December 2006, and Invited Talk at UC-Riverside, Feburary 2007. (pdf) |
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Last Updated 12/31/2006
