Lectures EE201A - Spring 2003 - Ingrid Verbauwhede

Lecture 1: Introduction

• Course Outline (PDF file)
• Motivation slides (PDF file)
• Reference: W.Strauss, "Digital Signal Processing, the New Semiconductor Industry Technology Driver," IEEE Signal Processing Magazine, pg. 52-56, March 2000. (PDF file)
• Reference: JPEG design experiment of EE201A Spring 2002 (PDF file)

Lecture 2: Properties of real-time embedded systems

• Properties of real-time embedded systems (PDF file)
• Reference: F. Catthoor, "Advanced processor architecture principles and design methodologies for multi-media applications"
  Section 1.3, 1.4, 1.5, (PDF file)
• Class presentation by Herwin and Yusuke:
  Introduction to TCP/IP (PDF file) (PPT file)

Lecture 3

• Modeling: Synchronous data flow graphs (PDF file)
• Reference: E.A. Lee, D. Messerschmitt, "Synchronous data flow," Proceedings of the IEEE, Vol. 75, no.9, Sept. 1987. (no softcopy so far)
• Class presentation:
• Reference: J. Kay, J. Pasquale, "Profiling and reducing processing overheads in TCP/IP," IEEE/ACM Transactions on Networking, Vol. 4, No. 6, Dec. 1996 (PDF file)

Lecture 4

• Modeling: multi-dimensional array representation in Phideo (PDF file)
• Reference: W. Verhaegh, et al. "A Two-Stage approach to Multidimensional Periodic scheduling," IEEE Transactions on CAD, Vol. 20, No. 10, October 2001, (PDF file of Journal paper)

Lecture 4bis: Presentation by V. Narayanan

• Prof. Vijay Narayanan of Penn State University, on "Memory management in embedded JVM's."
• Reference 1: "Heap compression for memory-constrained JAVA environments" (PDF file)
• Reference 2: "Energy savings through compression in embedded JAVA environments" CODES 2002 (PDF file)
• Reference 3: "Adaptive garbage collection" JVM 2002 (PS file) (PDF file)

Lecture 5

• Class presentation by Hao Yu, King-Ho Tam: (PDF file)
  Paper: P. Murthy, E.A. Lee, "Multi-dimensional Synchronous Data flow graphs" (PDF file)

Lecture 6

• Memory management: (PDF file)
• Class presentation by Nikos, Dustin: (Power point)
  Two Papers: (PDF file)

Lecture 7

• More on memory management: Atomium (PDF file)
  Reading: Chapter 3, "Exploration of global data transfer and storage organisation for decreased cost in data-dominated real-time systems". This is part of the course reader "Advanced architecture synthesis and compilation principles for multi-media applications," Author: Francky Catthoor, copyright: IMEC (PDF file)
• Class presentation by A. Vijayakumar and Doris Ching: A practical algorithm for exact Array dependency analysis (Power Point file)
  Paper: "A practical algorithm for exact Array dependency analysis" by William Pugh, Communications of the ACM, Vol. 35, no.8, August 1992. (PDF file)

Lecture 8

• Data dependency analysis and memory management (mostly notes on the board) (PDF file)

Lecture 9

• Presentation by Prof. Dan Gajski and Dr. Raimer Doemer: "System level design: system-on-chip environment" (PDF file)

Lecture 10

• Continue Memory management: loop transformations (PDF file)
• Class presentation by Xiong Liu & Roozbeh Jafari: Foreground memory management & link to graph theory (Power Point file)
  Paper:
  L. Stok, J. Jess, "Foreground memory management in datapath synthesis," Int. Journal of Circuit Theory and Applications, Vol. 20, pg. 235-255, 1992 (PDF file).

Lecture 11

• Gezel Design Environment by Patrick Schaumont (PDF file)
  Check also the Gezel webpage: (web link)

Lecture 12

• Memory Management - final (PDF file)
• Class presentation by SPECC language

Lecture 13

• Celoxica lecture by Doug Johnson (Powerpoint file)

Lecture 14

• DSP Processors: fundamentals (PDF file)
  Reference: E.A. Lee, "Programmable DSP Architectures: Part I", IEEE ASSP Magazine, Oct. 1988, pg. 4-19. (PDF file).
  Reference: E.A. Lee, "Programmable DSP Architectures: Part II", IEEE ASSP Magazine, Jan. 1989, pg. 4-14. (PDF file).
• Class presentation by Chun-Ching Tsan and Yung-Szu Tu on "Memory addressing organization for stream-based reconfigurable computing": (Powerpoint file)

Lecture 15

• DSP processors: more specifics (PDF file)
  Reference: E.A. Lee, "Programmable DSP Architectures: Part I", IEEE ASSP
• Class presentation by David Jea and Jessica Chou on "Hardware/Software instruction set configurability for system-on-chip processors" (Power Point file)
  Paper: A. Wang, E. Killian, D. Maydan, C. Rowen, "Hardware/software instruction set configurability for system-on-chip processors," Proceedings DAC 2001 (PDF file).

Lecture 16

• DSP processors: more specifics (cont.) (PDF file)
• Class presentation by Hui-Chun Wu, Yung-Shuo Lin: LisaTek (Power Point file)
  Reference Paper: A. Hoffmann et al., "A Novel Methodology for the Design of Application-Specific Instruction-Set (ASIPs) using a machine description language," IEEE Transactions on CAD, VOl. 20, no. 11, Nov. 2001. (PDF file).

Lecture 17

• DSP processors: Viterbi acceleration (PDF file)
  Reading: I. Verbauwhede, C. Nicol, "Low Power DSP's for Wireless communications," Proc. of the 2000 ISLPED, pg. 303-310, July 2000, (PDF file)
  A nice introduction to Viterbi is given in the following TI application note: (PDF file) SPRA071 document, available from www.ti.com
• Class presentation by Yan Lin and Lucanus Simonson: Daytona multi-unit DSP processor (Power Point file)
  Reference paper: B. Ackland et al, "A Single-Chip, 1.6Billion, 16-b MAC/s Multiprocessor DSP," IEEE JSSC, Vol 35, no. 3, March 2000, pg. 412-424. (PDF file)

Lecture 18

• DSP processors: VLIW architectures (PDF file)
• Class presentation by Wendong Hu, Bo-Kyung Choi, Hyun J. Moon: Networks on chip (Power Point file)
  Reference papers:
  1. L. Benini, G. DeMicheli, "Networks on chips: a new SOC paradigm," IEEE Computer Magazine, January 2002 (PDF file)
  2. P. Wielage, K. Goossens, "Networks on silicon: blessing or nightmare?" Proceedings of the Euromicro Symposium on Digital System Design (DSD'02) (PDF file)

Lecture 19

• No class: take home exam

Lecture 20

• Class presentation 1:
• Class presentation 2: