Reading Material EE215B - Ingrid Verbauwhede - Winter 2002

Lectures

• Lecture 1 - Introduction - Motivation
  - Rabaey, Chapter 1 - Introduction
  - S. Borkar, "Design Challenges of Technology Scaling", IEEE MICRO, Vol. 19, no.4 , pg. 23-29, July-Aug. 1999.
  - V. De, S. Borkar, "Technology and Design Challenges for Low Power and High Performance," Proceedings ISLPED 1999.
  - J. Meindl, "Low Power MicroElectronics: Retrospect and Prospect," Proceedings of the IEEE, Vol. 83, no. 4, April 1995
  Paper presentation in class
  - C. Svensson, "The limits to High-Speed Electronics," Proceedings ECOC 97, Sept. 1997.
• Lecture 2 - Scaling
  - Rabaey, Chapter 3 (new book) "The devices" or Chapter 2 (old book), "The devices",
  - B. Davari, R. Dennard, G. Shahidi, "CMOS scaling for High Performance and low Power - The next ten years" Proceedings of the IEEE, Vol. 83, no. 4, April 1995.
• BELOW ARE THE PAPERS FROM LAST QUARTER, AS WE GO THIS LINE WILL MOVE DOWN.
• Lecture 3 - The Wire
  - Rabaey, Chapter 4 (new book) "The wire" or Chapter 8 (old book) "Coping with Interconnect"
• Lecture 4 - Transmission lines
  - Rabaey, Chapter 4 (new book) "The wire" or Chapter 8 (old book) "Coping with Interconnect"
• Lecture 5 - S. Morton, "Techniques for driving interconnect."
  - Chapter 17 in "Design of High Performance Microprocessor circuits", A. Chandrakasan, W. Bowhill, F. Fox (Editors), IEEE Press, 2001.
• Lecture 6 - Coping with Interconnect
  - Rabaey, Chapter 8 (old book): "Coping with interconnect"
  - Background reading - excellent reference: H. Bakoglu, "Circuits, Interconnections and Packaging for VLSI" Addison Wesley, 1990.
• Lecture 7 - Circuit styles (combinational, ratio-ed, pass transistor)
  - Rabaey Chapter 4 (old book), Chapter 6 (new book) "Designing Combinational logic gates in CMOS"
  - DCVSL: L. Heller et al. "Cascode Voltage Swing Logic: A differential CMOS logic family," Proc. ISSCC, pp. 16-17, 1984.
  - SRPL: A. Parameswar, "A high speed, low power swing restored pass transistor logic based multiply and accumulate circuit for multimedia applications," Proc. CICC conference, pp. 12.5.1-12.5.4, May 1994.
• Lecture 8 - Circuit styles (cont.) Dynamic logic
  - LEAP: K. Yano et al. "Lean integration, Achieving a Quantum Leap in Performance and cost of logic LSIs" Proc. CICC Conf. San Diego, 1994.
  - P. Gronowski, "Issues in Dynamic Logic Design," Chapter 8 in "Design of High Performance Microprocessor circuits", A. Chandrakasan, W. Bowhill, F. Fox (Editors), IEEE Press, 2001.
• Lecture 9 - Midterm
• Lecture 10 - Power consumption in CMOS gates
  - Rabaey Chapter 4.4 (old book) or Chapter 6 (new book)
  - H. Veendrick, "Short-circuit dissipation on static CMOS Circuitry and its impact on the design of buffer circuits," IEEE Journal of solid state circuits, August 1984.
• Lecture 11 - Power Optimization
  - A. Chandrakasan, R. Brodersen, "Minimizing Power Consumption in Digital CMOS circuits," IEEE Proceedings, Vol. 83, no. 4, pp. 498-523, 1995.
• Lecture 12 - Sequential circuits
  - Rabaey Chapter 6 (old book) or Chapter 7 (new book) "Designing sequential logic circuits"
• Lecture 13 - Sequential circuits - cont.
  - B. Nikolic, et al., "Improved Sense-Amplifier-based Flip-Flop: design and measurments," IEEE Journal of Solid-State Circuits, Vol. 35, No. 6, June 2000.
  - S. Hesley, et al. "A 7th generation x86 Micro-processor," Proceedings of ISSCC, 1999, pg. 92-93.
  - H. Partovi et al., "Flow-through latch and edge-triggered flip-flop hybrid elements," Proceedings of ISSCC, 1996, pg. 138-139.
• Lecture 14 - Memory design
  - Rabaey Chapter 8 (old book)
• Lecture 15 -
  - W. Athas, et al. "The Design and Implementation of a Low-Power Clock-Powered Microprocessor," IEEE Journal of Solid-State Circuits, pg. 1561-1570, Vol. 35, no. 11, Nov. 2000
• Lecture 16 - Memory design (cont.)
  - Rabaey Chapter 8 (old book)
• Lecture 17 - Design for test
  - Rabaey Chapter 11 (old book)
• Lecture 18 and 19 - Project presentations