EE 215B - Ingrid Verbauwhede - Winter 2002

This emphasis of this course is on advanced circuit design for digital VLSI in state-of-the-art CMOS technologies. The goal is to link this to the underlying technologies (deep submicron) and to the usage of these circuit techniques in advanced applications (high performance micro-processors, ultra low power portable applications, heterogeneous systems on a chip).
Special focus of this quarter is on INTERCONNECT, NOISE and RELIABILITY. Class webpage is at link
Check last year's project webpage and last year's class webpage.

Mar 18, 2002: Finals are available for pick up from Letty's desk between 4 and 5pm (NO later than 5pm). Make sure to sign in when picking it up and sign again when dropping it off. Finals are due no later than 4.45pm Tuesday March 19, 2002.
Feb. 12, 2002: Midterms are available for pick up from letty's desk between 4 and 5pm. Make sure to sign in when picking it up and signing again when dropping it off.
Feb. 5, 2002: For any urgent questions regarding the project please contact Vaishnav (vaishnav@ee.ucla.edu) or see him in his cubicle (S15 on the 5th floor).
Jan. 25, 2002, Announcement from Vaishnav:
HW#2: For problem 2b) for downward transitions the coupled voltage is negative. In such cases it would be more instructive to plot this negative maximum as part of the histogram. So the histogram would have values ranging from the positive maximum to the negative maximum.