EE 215B - Ingrid Verbauwhede - Winter 2001

This emphasis of this course is on advanced circuit design for digital VLSI in state-of-the-art CMOS technologies. The goal is to link this to the underlying technologies (deep submicron) and to the usage of these circuit techniques in advanced applications (high performance micro-processors, ultra low power portable applications, heterogeneous systems on a chip).
Special focus of this quarter is on NOISE and RELIABILITY. Check the project webpage.

3/19/01: Problem 1 - Final - SRAM size is 8Kx8, not 8Kx8K.
Check the project webpage for all details!
Friday March 16, 2001, 2 to 4pm: 2nd set of presentation in room YOUNG 2018.
02/02/01: HW2 - Please use W= 1.2mm for the PMOS and W=0.4mm for the NMOS in this problem. This is milli-meter not micro-meter! Do NOT use a minimum size invertor. (Thanks to Dung Pham who figured out there are two different prints of Rabaey's book!)
01/31/01: HW2 - Spice models from back of Rabaey's book
01/15/01: HW1 - Problem 7.9 in Rabaey's book, Figure 7.50(a). The PMOS transistor above node C should be connected to node C, similar to all other PMOS transistors.