04/1999
"Interconnect Modeling and Optimization",
Electrical and Computer Engineering Department, 
University of  Illinois at Urbana-Champaign  

01/20/2000
"Interconnect Modeling and Optimization Considering On-Chip Inductance",
Electrical and Computer Engineering Department, 
Northwestern University 

05/26/2000
"Interconnect Modeling and Optimization Considering On-Chip Inductance",
Electrical and Computer Engineering Department, 
University of California, Santa Barbara

12/23/2000
"Modeling and Reduction of Microprocessor Power",
Hewlett Package Research Laboratories, Palo Alto, CA

02/23/2001
"Modeling and Reduction of Microprocessor Power",
Electrical Engineering Department, Stanford University

02/15/2001
"Modeling and Design of RLC Interconnects",
Intel Research Laboratories, Hillsboro, OR

03/15/2001
"Modeling and Design of RLC Interconnects",
Computer Aided Design Seminar, 
University of California, Berkeley

03/30/2001
"Interconnect Modeling and Optimization",
Cadence Berkeley Research Laboratory

05/07/2001  
"VLSI circuit design closure for signal integrity and power efficiency",
Computer Science Department, University of California, Irvine

05/25/2001
"Modeling and Design of RLC Interconnects",
IBM Research Laboratories, Yorktown Heights, NY

05/25/2001
"Modeling and Design of RLC Interconnects",
Bell Laboratories, NJ

12/08/2001
"Interconnect Planning and Design Considering Inductance",
Hewlett Package Research Laboratories, Palo Alto, CA