02/14/2002
"Modeling and Reduction of Leakage Power",
Intel Research Laboratories, Hillsboro, OR

02/21/2002
"VLSI Design Closure for Power Efficiency and Signal Integrity"
IBM Research Laboratories, Yorktown Heights, NY

12/23/2002
"FPGA Power Modeling and Reduction",
Electrical Engineering Department, Fudan University, Shanghai, China

01/21/2003
tutorial "Power and Signal Integrity in System-on-Chip Designs",
joint with Howard Chen (IBM) and Eli Chiprout (Intel)
at IEEE Asia South-Pacific Design
Automation Conference

02/21/2003
"Signal Integrity in System-on-Chip Designs",
SUN Microsystems, Sunnyvale, CA

05/09/2003
"Power and Signal Integrity for System-on-Chip",
Research Seminars, Cadence Design Systems, San Jose, CA

08/09/2003
"Power and Signal Integrity for System-on-Chip",
Electrical Engineering Department, University of Washington

02/13/2004
"FPGA Power Modeling and Reduction",
Research Seminar, Xilinx, San Jose, CA

03/18/2004
"Characteristics and Reduction of Microprocessor Leakage Power",
Research Seminar, Advanced Micro Devices, Austin, TX

03/19/2004
"Modeling and Management of the Interdependency between
Temperature and Leakage",
Weekly Seminars, IBM Research Laboratories, Austin, TA


04/12/2004
"Leakage modeling and reduction",
Electronic Systems Design Seminar, 
University of California, Berkeley


05/27/2004
"VLSI Circuit and System Design Closure Considering Power Efficiency
and Signal Integrity",
Fujitsu Research Laboratories, Sunnyvale, CA

06/08/2004
"System Level Leakage Reduction Considering Leakage and Thermal 
Interdependency", IEEE/ACM Design Automation Conference, 2004

08/28/2004
"Field Programmable Power Supply for FPGA Power Reduction",
Altera Research Seminars, Altera, San Jose, CA

09/24/2004
"Power Modeling and Reduction for Microprocessors",
Computer Science Department, Tsinghua University, Beijing, China

09/24/2004
"Power Characteristics and Reduction for Field Programmable Gate Arrays",
Computer Science Department, Tsinghua University, Beijing, China

10/04/2004
"Power Characteristics and Reduction for Field Programmable Gate Arrays",
Synopsys Research Seminars, Synopsys Corporation, Sunnyvale, CA

10/14/2004
"Power Characteristics and Reduction for Field Programmable Gate Arrays",
IBM CMOS Forum, Yorktown Heights, NY

11/23/2004
"Field Programmable Power Supply for FPGA Power Reduction",
National Science Foundation International Workshop on System-on-Chip, Hawaii

3/9/2005
"Voltage Scaling for Voice-over-IP with Quality of Service",
Corporate Search Seminar at Mindspeed Technology, CA. 

3/15/2005
"Circuits and Architectures for FPGA Power Reduction",
Corporate Search Seminar at Actel, CA. 

3/21/2005
"Package-Chip Co-Design: Strategies and Challenges," 
tutorial at IEEE/ACM International Symposium on Quality Electronic Design,
Co-speakers: L. Daniel (MIT) and B. Krauter (IBM).

08/08/2005
"Challenges and Opportunities for Low Power FPGAs in Nanometer Technologies," embedded tutorial, 
IEEE/ACM International Symposium on Low Power Electronics and Design, 
Co-speakers: M. Hutton (Altera), T. Tuan (Xilinx) and S. Wilton (UBC).

8/31/2005
"FPGA Architecture Considering Process Variations,"
Research Seminar, Xilinx, San Jose, CA