Rani S. Ghaida

Personal Webpage

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Patents

P1. R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, and S. R. Nassif, “Pin-access maximization under manufacturing constraints,” pending, submitted on Oct. 2011.

P2. R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, and S. R. Nassif, “Mask assignment for multiple patterning lithography,” pending, submitted on Sep. 2011.

P3. R. S. Ghaida, K. B. Agarwal, L. W. Liebmann, and S. R. Nassif, “Multiple patterning layout decomposition for ease of conflict removal,” pending, submitted on Sep. 2011.

P4. R. S. Ghaida and K. B. Agarwal, “Resolving double patterning conflict,” pending, submitted on Jul. 2011.

P5. R. S. Ghaida and P. Gupta, “Single-mask double-patterning lithography,” pending, submitted on Mar. 2010.

Refereed Journal Publications

J1. R. S. Ghaida and P. Gupta, “DRE: a framework for efficient and systematic co-evaluation of design rules, technology choices, and layout methodologies,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD),, accepted, 2012 [pdf].

J2. R. S. Ghaida, G. Torres, and P. Gupta, “Single-mask double-patterning lithography for reduced cost and improved overlay control,” IEEE Trans. Semiconductor Manufacturing, vol. 24(1), pp. 93-103, Feb. 2011 [pdf].

J3. R. S. Ghaida and P. Gupta, “Within-layer overlay impact for design in metal double patterning,” IEEE Trans. Semiconductor Manufacturing, vol 23(3), pp. 381-390, Aug. 2010 [pdf].

J4. R. S. Ghaida, K. Doniger, P. Zarkesh-Ha, “Yield prediction based on a stochastic layout sensitivity model,” IEEE Trans. Semiconductor Manufacturing, vol. 22(3), pp. 329-337, Aug. 2009 [pdf].

J5. R. S. Ghaida and P. Zarkesh-Ha, “A layout sensitivity model for estimating electromigration-vulnerable narrow interconnects,” Journal of Electronic Testing: Theory and Applications, vol. 25(1), page 67, Feb. 2009 [pdf].

 

Peer-Reviewed Conference Publications

C1. R. S. Ghaida K. B. Agarwal, L. W. Liebmann, S. R. Nassif, and P. Gupta, “A novel methodology for triple/multiple-patterning layout decomposition,” SPIE Advanced Lithography— Design for Manufacturability through Design-Process Integration III, to appear, Feb. 2012 [pdf].

C2. R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, “A framework for double patterning-enabled design,” Intl. Conference on Computer-Aided Design (ICCAD), Nov. 2011 [pdf].

C3. A. R. Neureuther et al., “Collaborative research on emerging technologies and design,” SPIE Photomask Japan— Photomask and Next-Generation Lithography Mask Technology, Apr. 2011 [pdf].

C4. T.-B. Chan, R. S. Ghaida and P. Gupta, “Electrical modeling of lithographic imperfections,” IEEE Intl. Conf. on VLSI Design, Jan. 2010 [pdf].

C5. R. S. Ghaida and P. Gupta, “A framework for early and systematic design rule evaluation,” Intl. Conference on Computer-Aided Design (ICCAD), Nov. 2009 [pdf].

C6. R. S. Ghaida, G. Torres, and P. Gupta, “Single-mask double-patterning lithography,” SPIE/BACUS Photomask Technology, vol. 7488, Sep. 2009 [pdf].

C7. R. S. Ghaida and P. Gupta, “Design-overlay interactions in metal double patterning,” SPIE Advanced Lithography— Design for Manufacturability through Design-Process Integration III, vol. 7275, Feb. 2009 [pdf].

C8. R. S. Ghaida and P. Zarkesh-Ha, “Estimation of electromigration-aggravating narrow interconnects using a layout sensitivity model,” IEEE Intl. Symp. on Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07, page(s):59 — 67, September 2007 [pdf].

 

Workshops/Conferences with Unpublished Proceedings

W1. R. S. Ghaida and P. Gupta, “A framework for systematic evaluation and exploration of design rules,” SRC TECHCON, Sep. 2009.

 

Software

S1. R. S. Ghaida, “UCLA_DRE design rule evaluator,” Directed by P. Gupta, Aug. 2009 [project's webpage].

Theses

T1. R. S. Ghaida, “Semiconductor yield analysis and prediction using a stochastic layout sensitivity model,” University of New Mexico, Master’s Thesis, December 2007 [pdf].

T2. R. S. Ghaida, “A different approach to fabricating three-dimensional integrated circuits,” Lebanese American University, Undergraduate Thesis, October 2005 [brief, full report].

Publications