Circuit Techniques for High-Speed Communication Systems

The rapid increase in the demand for broadband data communication systems has motivated extensive research on higher-speed, higher-integrated solutions with lower cost and lower power consumption. This research deals with architecture and circuit design as well as theoretical modeling for such applications. First, we propose an analysis of regenerative dividers that predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded divide-by-two stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply. Next, we present a 40-Gb/s phase-locked clock and data recovery circuit incorporating a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly-spaced points, providing half-quadrature phases. The phase detector employs eight flipflops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-um CMOS technology, the circuit produces a clock jitter of 0.9 ps-rms and 9.67 ps-pp with a PRBS of 2^31-1 while consuming 144 mW from a 2-V supply. Finally, a large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts such characteristics of clock and data recovery circuits as jitter transfer, jitter tolerance, jitter generation, bit error rate, and capture range. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

High-speed CMOS circuits for gigabit ethernet on copper wire

The next generation of local area networks (LANs) operates at data rates of up to several hundred megabits, or gigabits per second. In order to minimize the cost, use of the existing unshielded twisted-pair cable (similar to telephone copper wire) to connect the network terminals to central hubs is desirable. Among all of the LAN standards, Gigabit Ethernet on category 5 unshielded twisted pair (UTP) is the most popular and economical, since it is the next generation standard of commonly-used 10/100Base-T Ethernet. Due to the high data bandwidth on medium-quality copper line, and simultaneous data transmission on four twisted-pair cables, advanced signal processing such as channel equalization and echo/crosstalk cancellation is required to recover the signal from noisy channels. In order to meet the stringent bit-error-rate specifications of Gigabit Ethernet, designers of 1000Base-T must use complex digital signal processing as well as high resolution A/D converters to reduce impairments due to highly-corrupted channels. Until now, full digital signal processing has been considered the only possible solution to implement 1000Base-T transceivers. This research has investigated analog adaptive circuits to cancel noise and perform channel equalization in the analog front end. In addition to the circuit implementation, a custom C program is written to emulate the transceiver in order to determine the specifications of each analog building block. An adaptive mixed-signal echo canceller and a linear channel equalizer are proposed in this work to boost the signal-to-noise ratio. With the aid of these two building blocks, the A/D converter design requirement and the digital signal processor complexity are both reduced. In contrast to fully digital or analog implementations, the Gigabit Ethernet transceiver can be implemented by lower power consumption and smaller silicon die size with this hybrid architecture.

A low-power 2.4-GHz CMOS transceiver for wireless LAN applications

The rapid increase in the demand for RF transceivers used in wireless LAN systems such as Bluetooth and IEEE 802.11b has motivated extensive research on low-power solutions. This research deals with architecture, circuit, and device design for such applications. A multistandard CMOS transceiver incorporates low-power RF and analog techniques while operating with both frequency-hopped and direct-sequence systems. Using a single 1.6-GHz synthesizer, the circuit incorporates two downconversion and upconversion stages while providing on-chip image-rejection filtering. The transceiver employs on-chip stacked inductors extensively. With a modification of stacked spirals, the self-resonance frequencies increase by 100%, allowing high value inductors. Realized in a 0.25-um digital CMOS technology, the transceiver (excluding the synthesizer) consumes 17.5 mW from a 2.5-V supply.

High-speed clock and data recovery circuits for random non-return-to-zero data

The rapid increase of real-time audio and video transport over the internet has led to a global demand for high-speed serial-data communication networks. To accommodate the required bandwidth, an increasing number of wide area networks (WANs) and local area networks (LANs) are converting the transmission medium from a copper wire to fiber. This trend motivates research on low-cost, low-power integrated fiber-optic receivers. A critical task in such receivers is the recovery of the clock embedded in the non-return-to-zero (NRZ) serial-data stream. The recovered clock both removes the jitter and distortion in the data and retimes it for further processing. The research objective of this thesis is to analyze, design, and implement highspeed clock and data recovery circuits for 2.5-Gb/s optical fiber receivers that can be readily implemented in an integrated, low-cost, low-power CMOS technology. Our primary contributions to this research include the design methodology and implementation of two clock recovery circuits fabricated in both 0.4-um and 0.25-um digital CMOS technologies without the aide of external references. The circuit designed in the 0.4-um CMOS is limited by the achievable technology bandwidth. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide tuning range. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS of length 2^7-1. The core circuit dissipates a total power of 33.5 mW from 3.3-V supply and occupies an area of 0.8 x 0.4 mm^2. The system design in the 0.25-um CMOS includes both a frequency-locked loop (FLL) loop as well as a phase-locked loop (PLL) to increase the frequency acquisition range of the circuit with no external reference. To achieve a wide tuning range with low phase noise, an LC-oscillator is employed with a digital capacitor array. The recovered clock exhibits an rms jitter of 5.1 ps for a PRBS of length 2^23-1. This circuit core dissipates 55 mW of power from a 2.5 V supply and occupies a core area of 0.9 x 0.6 mm^2.

A 2-GHz CMOS image-reject receiver with sign-sign LMS calibration

This dissertation describes a sign-sign least-mean squares (LMS) technique to calibrate gain and phase errors in the signal path of a Weaver image-reject receiver. The calibration occurs at startup and the results are stored digitally, allowing continuous signal reception thereafter. Fabricated in a standard digital 0.25-um CMOS technology, the receiver achieves an image-rejection ratio of 57 dB after calibration, a noise figure of 5.2 dB, and an IIP3 of −17 dBm. The circuit consumes 55 mW in calibration mode and 50 mW in normal receiver mode from a 2.5-V power supply. The prototype occupies an area of 1.23 x 1.84 mm^2.

A 10-Gb/s CMOS clock and data recovery circuit

With the exponential growth of the number of Internet nodes, the volume of the data transported on the backbone has increased with the same trend. The load of the global Internet backbone will soon increase to tens of terabits per second. This indicates that the backbone bandwidth requirements will increase by a factor of 50 to 100 every seven years. Transportation of such high volumes of data requires suitable media with low loss and high bandwidth. Among the available transmission media, optical fibers achieve the best performance in terms of loss and bandwidth. High-speed data can be transported over hundreds of kilometers of single-mode fiber without significant loss in signal integrity. These fibers progressively benefit from reduction of cost and improvement of performance. Meanwhile, the electronic interfaces used in an optical network are not capable of exploiting the ultimate bandwidth of the fiber, limiting the throughput of the network. Different solutions at both the system and the circuit levels have been proposed to increase the data rate of the backbone. System-level solutions are based on the utilization of wave-division multiplexing (WDM), using different colors of light to transmit several sequences simultaneously. In parallel with that, a great deal of effort has been put into increasing the operating rate of the electronic transceivers using highly-developed fabrication processes and novel circuit techniques. The design of the clock and data recovery (CDR) circuit is the most challenging part of building a high-speed optical transceiver because of the complexity of this block. In this dissertation, the design and experimental results of two CDR circuits are described. Both the circuits achieve a high operating speed by employing the concept of "half rate", meaning that the clock frequency is half the data rate. Furthermore, broadband circuit techniques including wideband amplification and highspeed matched filtering are described in this dissertation. The two circuits benefit from two major techniques for phase detection, namely linear and binary. The design of the linear phase detector is based on a new technique that allows a fast speed and low power consumption because of its simplicity. The new binary phase/frequency detector provides a wide capture range and a phase error signal that is only revalidated at data transitions. Furthermore, the design of the CDR circuits involves utilization of two major types of voltage-controlled oscillators, which are ring and LC-tuned. The ring oscillator described in this work achieves a wide tuning range and low power consumption. The LC oscillator benefits from a new topology that provides multiple phases with low jitter.