• Homework 6. Tuesday Due 6/4/2002, 12 o'clock noon at Letty's desk (Boelter 7440)

  This is teamwork as always. The homework (PDF) will take your design into implementation using one of the implementation platforms for C54, BlackFin, ART or DK1. The results to be reported include the speed of your design, as well as the area (memory footprint or clb count). Power consumption estimates/ measurements are appreciated as well such that you can give a ballpark for the number of JPEG block encodings per Joule.

• Homework 5.

  The homework (PDF) can be solved in teams of two persons as always. There is a package from which you can start.

  This homework will take the JPEG model into implementation. Implementation here means a C program. However, unlike the initial C++ model that you worked with, the C program you create now will be optimized for the target platform (which is one of BlackFin, C54, VirtexII or ART-ASIP depending on the team you are in). The previous steps in the project have given you a good understanding of how JPEG works. One of the main design difficulties is that JPEG works with images (multidimensional data), and requires judicious use of arrays and memory in order to maintain high performance. Now, we will use the Atomium tool to collect feedback on how well we write C implementation code. Atomium creates an instrumented version of your C program and gives you feedback on the number of accesses per array variable.

  The software package from which you start requires you to work on an HPUX10 machine from the HP lab. Don't forget to read the 'how to start' section from the homework before you start (you need to set an environment variable) ! The package contains a version of the JPEG dataflow model that can be processed by Atomium. It serves as a starting point from which you can create optimized C code. Run the compilation with 'make' to see how Atomium is called, and how your program should be compiled.

  If you are stuck at any moment, please use the board to ask questions.

• Homework 4.

  To solve the homework (PDF) you can work in teams of two persons. Check the teams to find which environment to use. The software package that you need for the homework is provided as a tar package. To use it, you will need a C++ compiler. For use of ART Library, you will need to work on the HP-lab machines.

  As always, the board is there to help you.

• Homework 3.

  This homework (PDF) is 2-person as usual. You will use one of HandleC, SpecC, or SystemC to solve it. Check the teams to check which environment to use.

  The homework requires you to get into a new environment and work with new tools. Take one step at a time, and start by first looking into some HandleC, SpecC or SystemC programming examples. If you get stuck at any moment, especially as it concerns pragmatics ('my machine X witth compiler Y does not run Z'), post the problem on to the board. It's there to help you !

• Homework 2.

  To solve the homework (PDF) you can work in teams of two persons. You will need a C++ compiler to solve it, as will as a package with the JPEG reference model. Please make sure that you compile the package and run a simulation. Once we get to the implementation part, such a golden model will be very useful.

  The reference model reads in images of the PPM format and writes out JPEG files. There are some reference images provided with this package. Both PPM and JPEG are supported by most picture and image processing software. Examples of such software are irfanview (Windows) and Gimp (Unix). If you want to create your own images, you can use a bitmap editor such as the Paint tool under windows or Gimp. The JPEG standard is described in ITU-81.

  Questions and issues can be posted to the class bulletin board.

• Homework 1.

  To solve the homework you can work in teams of two persons. You will need a C compiler and a Verilog simulator to solve it. You are free to use your preferred C compiler. The code that you turn in must compile (and run) under gcc, the GNU C compiler. The homework assignment is available as a pdf file that explains the problem and tells what to turn in. The Verilog and C code to start from is available as a package hw1.tar.

  The application considered in the homework is DES, the Data Encryption Standard. Follow the link to a short description of the operation of DES. For the full works consider the Handbook of Applied Cryptography by Menzenes, Chapter 7. Be sure however to focus on the core question of the homework, which is: how much can you improve the simulation speed of a bitlevel Verilog simulation by recoding an equivalent simulation in C ?

  Questions and issues can be posted to the class bulletin board.

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Resources

Using the BlackFin DSP from Analog Devices at UCLA for EE201A

The development environment for the BlackFin DSP is called Visual DSP++. This environment contains a C compiler, assembler, linker as well as an instruction set simulator for the BlackFin DSP. It includes detailed profiling analysis tools such as source code profiling and pipeline visualization. For Blackfin targets, this environment will be used to design and debug the JPEG. You can download the environment from the website (free registration required). You need a PC with Windows to install it. If you don't want to wait for long downloads, we have also an evaluation CDROM. Post a message on the board when you want to use it.

An excellent source of information on development with the BlackFin DSP is the web site of Dr Mike Smith from the University of Calgary.

In Lab 53-109, Engineering IV, we have set up an evaluation board as well. When your JPEG design is completed, it can be tested on the actual chip.

Using the TI C5X DSP from Texas Instruments at UCLA for EE201A

The development environmebt for the C54 DSP is called Code Composer C5000 This environment contains a C compiler, assembler, linker as well as an instruction set simulator for the TI C54 DSP. You can download it from their website (registration required). You need a Windows PC to install it.

We have also a few development kits available that you can use for the project. This requires you to have a Windows PC at the UCLA. You will also have to sign for reception of such a kit and return it at the end of the course before the finals. Post a message on the board when you want to make use of this option.

In Lab 53-109, Engineering IV, we have set up an evaluation board as well. When your JPEG design is completed, it can be tested on the actual chip.

Using ART Designer from Adelante Technologies at UCLA for EE201A

The ART Designer environment is available on HP/UX in the HP-Lab. Since 10 weeks is too short to do a full ASIC implementation, we will work with a Xilinx FPGA backend for prototyping. Check the slides of Doug Jhonson's presentation again as well as the ART homework.

You can use the Xilinx Webpack as FPGA backend. It contains synthesis and simulation for Verilog as well as place and route. You will need a Windows PC to do the installation.

In Lab 53-109, Engineering IV, we have set up an evaluation board as well. When your JPEG design is completed, it can be tested on the actual chip.

Using HandleC + Xilinx Virtex-II at UCLA for EE201A

The DK1 environment from Celoxica already in use for HW3 will be used for the next phases of the project as well. The Academic version that we use does not contain HDL code generation. However, it returns metrics with respect to the complexity of your design, so you will be able to continue developments in Academic until the very end. We also have a limited number of full versions of HandleC/DK1 that we will make available to groups targetting HandleC.

You can use the Xilinx Webpack as FPGA backend. It contains synthesis and simulation for Verilog as well as place and route. You will need a Windows PC to do the installation.

In Lab 53-109, Engineering IV, we have set up an evaluation board as well. When your JPEG design is completed, it can be tested on the actual chip.

Using SystemC, SpecC or HandleC at UCLA for EE201A

In the next table, you find the availability of design environments at UCLA. The procedure for getting started is essentially this. Check the teams list to find which environment you have to use for the next project phase. For example, Team 1 (Bocheng and Kazuo) will use SpecC.

Next, consider the table below to select a platform that you can use. 'bin' means an executable is available, 'src' means you will have to compile the environment from source, and 'x' means the environment is not available on that platform. Platforms are PC (Win), SUN (Solaris), PC (Linux) and HP (HPUX). Win (Cygwin) is a windows-PC environment that has the Cygwin environment installed. Win (MSC) is a windows-PC environment that has the Microsoft Visual C++ compiler installed.

SystemC can be downloaded from the web. Membership to the SystemC Users Group is required. Membership is free, and it is a good idea anyhow since you will be able to access a lot of extra information on the SystemC language. You will have to compile the SystemC library yourself. Be sure to test some of the examples included before you start doing developments yourself.

SpecC can be downloaded from the web, too. The SpecC site offers both binaries as well as source code for the SpecC reference compiler. For hassle-free installation, consider using the binary version of the tool before using source code.

Teams running HandleC must choose a time on MONDAY APRIL 22 when the Handle-C software will be installed on their computer. As we have only one CDROM, I will make a tour to do installation that day. I assume you have a PC running windows and one of Cygwin or MSC with 20 Megabytes harddisk space free. Choose your time by posting a message on the "Projects-2" bulleting board. When you do the post, please check for conflicting times.

		SpecC	SystemC	HandleC
	Win (Cygwin)	bin/src	src	bin
	Win (MSC)	x	src	bin
	Solaris	bin/src	src	x
	Linux	bin/src	src	x
	HP UX	x	x	x

JPEG Reference information

• Functional Specification
  • Class Presentation on JPEG by Michael Chou ∓ Scott Siegrist
  • ITU-81, the official JPEG standard
  • Reference Implementation of a 422 baseline JPEG encoder in C++
• Implementation on DSP
  • Texas Instruments AN spra644: JPEG for Digital Panel on the TMS320C5000
  • Texas Instruments AN spra621: Implementing JPEG with TMS320C2xx Assembly Language Software
• Implementation in Hardware
  • 4i2i Communications MJPEG Encoder/Decoder IP Core (datasheet)

Support Software and Information

• Cygwin: a unix environment on top of Windows.
  This will give you a gcc/g++ compiler on your Windows PC without the hassle of switching operating systems.
• IrfanView: Image viewing and format conversion software.

The following is a list of design environments relevant to the course that can be obtained quite easy. You are encouraged to take a look at them. Some of them will also be used in class projects.

Specification Environments

• Synopsys: Simulator for SystemC
• UC Irvine: Reference Compiler for SpecC
• CMA,Inria: Simulator for Esterel
• Celoxica: Handle-C Simulator for Handle-C

FPGA Design Environments

• Xilinx Virtex, Spartan: Webpack
• Altera APEX, FLEX: Quartus II

Fixed-Point DSP Core Design Environments

• Analog Devices Blackfin DSP: VisualDSP++
• Texas Instruments C54 DSP (RISC): Code Composer Studio for C5000
• Texas Instruments C6000 DSP (VLIW): Code Composer Studio for C6000

Custom ASIP Environments

• Adelante: ART Designer - VLIW Architectures: On EEnet
• Tensilica: Xtensa

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Teams

		Names	Spec	Design	Platform
	Team 1	Bocheng Lai Kazuo Sakiyama	SpecC	Visual DSP++	DSP/BlackFin
	Team 2	Henry Lau Gee Hang Lui	HandleC	Code Composer	DSP/C54
	Team 3	Sungha Kim Rupesh Goel	SystemC	ART Designer	ASIP
	Team 4	Hanish Rathod Hui Li	SystemC	ART Designer	ASIP
	Team 5	Scott Siegrist Michael Chou	SpecC	Code Composer	DSP/C54
	Team 6	Eric Yee Tom Hsieh	HandleC	DK1	FPGA/Virtex
	Team 7	Raghu Rao Jatin Bhatia	SystemC	ART Designer	ASIP
	Team 8	Heemin Park Arun A Somasundara	SystemC	ART Designer	ASIP
	Team 9	Young H Cho Shiva Navab	SpecC	Visual DSP++	DSP/BlackFin
	Team 10	Yen Cheng Kuan Eric Chim	HandleC	DK1	FPGA/Virtex
	Team 11	Eric Kwan Sandeep Vardham	SpecC	Visual DSP++	DSP/BlackFin
	Team 12	Alireza Hodjat Yi Fan	HandleC	DK1	FPGA/Virtex
	Team 13	Vijay Raghunathan Ramkumar Rengaswamy	SpecC	Code Composer	DSP/C54

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This page is maintained by Patrick Schaumont (schaum@ee.ucla.edu)