Heterogeneous Integration on Silicon-Interconnect Fabric using Fine Pitch Interconnects (≤10 µm)

Speaker: SivaChandra Jangam
Affiliation: Ph.D. Candidate

Via Zoom:  https://ucla.zoom.us/j/91970889530?pwd=b0t5MUZQcVNDNTAvNWhucEZHRHloZz09

Abstract:   Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent slow-down of Moore’s law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 µm) using fine-pitch (≤10 µm) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 µm pitch interconnects with a low specific contact resistance of ≤0.7 Ω-µm2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 µm) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes.

Biography:  SivaChandra Jangam received his Bachelor of Technology degree in Electrical Engineering from Indian Institute of Technology Kanpur, (IIT Kanpur) India and Master of Science in Electrical Engineering from the University of California, Los Angeles (UCLA). He is currently pursuing his Ph.D. degree at UCLA, working with Prof. Subramanian Iyer as a part of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). His research interests include heterogeneous integration, system scaling, and advanced packaging. His doctoral research was on the development of the Silicon Interconnect Fabric (Si-IF) technology which is a fine-pitch (10 µm), high-bandwidth (8 Tbps/mm), low latency (30 ps), low power (0.03 pJ/b) heterogeneous integration platform.

Siva is the recipient of the Electronics Packaging Society (EPS) Ph.D. fellowship 2019, the Guru Krupa Fellowship 2017, and the department fellowship for “Outstanding performance in Ph.D. preliminary exam.”   He was also awarded the “Intel Best Student Paper” in the 2017 Electronic Components and Packaging Conference (ECTC), and the “Outstanding student paper award” in the 2018 International Microelectronics Symposium (IMAPS).

For more information, contact Prof. Subramanian Iyer ()

Date/Time:
Date(s) - Jun 02, 2020
2:00 pm - 4:00 pm

Location:
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