Low-Power Techniques for CMOS Wireline Receivers

Speaker: Abishek Manian
Affiliation: Ph.D. Candidate - UCLA

Ph.D. Defense

Abstract:  With the ever-increasing need for high throughput from chip-to-chip I/Os, wireline transceivers are being pushed to operate at higher speeds. With the increase in data rates, the power consumption of broadband receivers has become critical in multi-lane applications like the Gigabit Ethernet. It is therefore desirable to minimize the power drawn by all of the building blocks.

This work introduces a 40-Gb/s CMOS wireline receiver that advances the art by achieving a tenfold reduction in power and an efficiency of 0.35 mW/Gb/s. An innovative aspect of the proposed NRZ receiver is our “minimalist” approach, which recognizes that every additional stage in the data or clock path consumes more power and limits the bandwidth. The minimalist mentality avoids multiple stages in the front-end continuous-time linear equalizer (CTLE), quadrature oscillators in the clock and data recovery (CDR) circuit, clock or data buffers, or phase interpolation. Moreover, building blocks are shared among different functions so as to reduce the number of current paths between V_DD and ground. Using charge-steering techniques extensively, the receiver contains only a few static bias currents adding up to about 6 mA. The minimalist approach also leads to a small footprint, about 110 µm x 175 µm, for the entire receiver, making it possible to design a multi-lane system in a small area and with short interconnects.

This receiver incorporates a one-stage CTLE with 5.5-dB boost, a one-tap discrete-time linear equalizer (DTLE) with 5.4-dB boost, a half-rate CDR circuit, a two-tap half-rate/quarter-rate decision-feedback equalizer, a 1:4 deserializer, and two new latch topologies. Since in recent designs, the CTLE draws significant power, this work introduces the DTLE as an efficient means of creating a high-frequency boost with only 0.3 mW. Fabricated in 45-nm CMOS technology, the receiver achieves a BER < 10^-12 with a recovered clock jitter of 0.515 ps_rms, a jitter tolerance of 0.45 UI at 5 MHz, with a channel loss of 18.6 dB at Nyquist, while consuming 14 mW from a 1-V supply.

Biography: Abishek Manian received his B.E. degree in Electronics and Telecommunication from University of Mumbai, India, in 2011, and his M.S. degree in Electrical Engineering from University of California, Los Angeles, in 2013. He is currently a Ph.D. candidate in the Department of Electrical Engineering under Prof. Behzad Razavi. His research interests include analog/mixed-signal circuit design for wireline transceivers.

For more information, contact Prof. B. Razavi (razavi@ee.ucla.edu)

Date/Time:
Date(s) - Mar 16, 2016
9:00 am - 11:00 am

Location:
E-IV Maxwell Room #57-124
420 Westwood Plaza - 5th Flr. , Los Angeles CA 90095