Speaker: Michael Orshansky
Affiliation: University of Texas at Austin
Abstract: Approximate computing aims to achieve energy savings at the cost of reduction in the accuracy of computation. The talk describes several results in modeling and synthesis of approximate circuits. We first propose a model of energy-optimal approximate addition achieved through timing starvation. We identify a fundamental trade-off between error frequency and error magnitude in a timing-starved adder and introduce a formal model to prove that for signal processing applications reducing bit-wise error frequency is sub-optimal. We also show how to synthesize an approximate Boolean network using the Boolean relations (BR) minimization problem and the recently developed fast algorithms for BR. We then show how the existence of an intrinsic notion of quality floor present in typical digital signal processing circuits can be used to reduce their energy consumption by strategically accepting some runtime errors under scaled supply voltage. The introduced innovations include techniques for carefully controlling possible errors and exploiting the specific patterns of errors for low-cost post-processing to minimize image quality degradation. Finally, we present a first adaptation and hardware realization of a new dimensionality reduction technique based on random projection. The technique performs approximate dimensionality reduction of large matrices at the cost of controlled accuracy loss. Operating on data projected into reduced dimension can decrease the computational complexity by orders of magnitude. Experimental results on an FPGA show that a face reconstruction algorithm utilizing the proposed accelerator of random projection achieves an up to 5X speed-up while maintaining a similar level of accuracy compared to the standard singular value decomposition approach.
Biography: Michael Orshansky is a Professor of Electrical and Computer Engineering at the University of Texas at Austin and holds the John E. Kasch Endowed Faculty Fellowship in Engineering. His research interests include low-power design, hardware security, approximate computing, design optimization for robustness and manufacturability, and statistical analysis and design methods. He has published over 90 technical articles and holds three U.S. patents. He is the author of the book “Design for Manufacturability and Statistical Design: A Constructive Approach.” He has served as an Associate Editor for the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on VLSI. He is the recipient of a number of awards for his research contributions and professional services, including the National Science Foundation CAREER award in 2004, ACM/SIGDA Outstanding New Faculty Award in 2007, ACM Recognition of Service Award in 2007, University of Texas Faculty Research Award in 2004, IEEE Transactions on Semiconductor Manufacturing Best Paper Award in 2004, Best Paper Award at the Design Automation Conference in 2005, Best Paper Award at the International Symposium on Quality Electronic Design in 2006, and IEEE/ACM William J. McCalla Best Paper Award at the International Conference on Computer-Aided Design in 2006. He is a Fellow of IEEE.
For more information contact Professor Behzad Razavi ()
Date(s) - May 02, 2016
1:00 pm - 2:00 pm
EE-IV Shannon Room #54-134
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095