Speaker: Eby Friedman
Affiliation: University of Rochester

Abstract:  The focus of this presentation is on the fundamental challenges in delivering power to high speed, high complexity heterogeneous integrated circuits. The efficient generation and distribution of multiple on-chip power supply voltages require fundamental changes to the power delivery process to provide increased current in next generation nanoscale heterogeneous integrated

The delivery of high quality power to the on-chip circuitry with minimum energy loss is a fundamental objective of all modern integrated circuits (ICs). To supply sufficient power on-chip, a higher unregulated DC voltage is usually stepped down and regulated within the power delivery system. Power conversion and regulation resources should be efficiently managed to supply high quality power with minimum energy losses within multiple on-chip power domains. The design complexity of a power delivery system increases with greater requirements on the quality of the power supply, limitations of the passive elements, board and package parasitic impedances, and limited number of I/O pins. Furthermore, to satisfy challenging power efficiency and regulation requirements, hundreds of power regulators should be co-designed with thousands of decoupling capacitors, distributing the power locally to billions of on-chip

With the introduction of ultra-small on-chip voltage regulators, there is a need for novel design methodologies to determine the location of these on-chip power supplies and decoupling capacitors. A codesign methodology is presented to simultaneously determine the optimal location of the power supplies and decoupling capacitors within a high performance power delivery network. The effects of the size, number, and location of the power supplies and decoupling capacitors on the power noise are also discussed.  These circuits, algorithms, and design methods will fundamentally change the manner in which power is delivered on-chip, producing a more efficient methodology for generating, distributing, and managing power to the billions of components within a high performance heterogeneous integrated system.

Biography:  Eby G. Friedman received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering.  He is the author of more than 500 papers and book chapters, 14 patents, and the author or editor of 18 books in the fields of high speed and low power CMOS  design techniques, 3-D design methodologies, high speed interconnect, and the theory and  application  of  synchronous  clock  and power distribution networks. Dr. Friedman is the Editor-in-Chief of the Microelectronics Journal, a Member of the editorial boards of the Journal of Low Power Electronics and Journal of Low Power Electronics and Applications, and a Member of the technical program committee of numerous conferences.

He previously was the Editor-in-Chief and Chair of the Steering Committee of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the Regional Editor of the Journal of Circuits, Systems and Computers, a Member of the editorial board of the Proceedings of the IEEE, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Analog Integrated Circuits and Signal Processing, and Journal of Signal Processing Systems, a Member of the Circuits and Systems (CAS) Society Board of Governors, Program and Technical chair of several IEEE  conferences, and  a  recipient of the IEEE Circuits and Systems Charles A. Desoer Technical Achievement Award, a University of Rochester Graduate Teaching Award, and a College of Engineering Teaching Excellence Award. Dr. Friedman is a Senior Fulbright Fellow and an IEEE Fellow.

For more information, contact Prof. Subramanian Iyer ()

Date(s) - Aug 01, 2017
11:00 am - 12:00 pm

E-IV Maxwell Room #57-124
420 Westwood Plaza - 5th Flr. , Los Angeles CA 90095