The Development of Interconnect Technology

Speaker: Eric Perfecto
Affiliation: GlobalFoundries

Abstract:  This talk will discuss interconnect technology for advanced flip chip packaging. We will discuss the under-bump metallurgy and solder selection and deposition methods. We will trace the development of Copper pillar technology and the flip-chip assembly process using both mass reflow and thermal compression. Finally we will discuss Chip-Package interaction and other failure modes. Finally we will discuss bumpless Flip-chip with RDLs.

Biography:  Eric Perfecto has 34 years of experience working in the development and implementation of advanced packages. He is currently Principal Member of the Technical Staff at GLOBALFOUNDRIES. Previously, he served as C4 Development Chief Technologist at IBM responsible for UBM and Pb-free solder definition for u-Pillar interconnect, and yield improvements in C4 and 3D wafer finishing. His technical interests include flip chip, 2.5 & 3D fabrication, chip-package interaction, electro-migration, multi-level Cu-Polymer wiring structures, and design for manufacturing. He holds a M.S. in Chemical Engineering from the University of Illinois and a M.S. in Operations Research from Union College. Eric has published over 75 external papers, including two best Conference Paper Awards (2006 ESTC and 2008 ICEPT-HDP) and the 1994 Prize Paper Award from CMPT Trans. on Adv. Packaging. He holds over 45 US patents, and has been honored with two IBM Outstanding Technical Achievement Awards. Eric was the 57th ECTC General Chair in Reno, NV, and the Program Chair at the 55th ECTC.  He is an IEEE, IMAPS and Society of Plastic Engineers senior, an elected BoG member of CPMT Society of IEEE and a CPMT Distinguish Lecturer. He is also the CPMT Awards Program Director.

For more information, contact Prof. Subramanian Iyer ()

Date/Time:
Date(s) - Apr 26, 2016
2:00 pm - 6:00 pm

Location:
EE-IV Shannon Room #54-134
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095