CONFERENCES
[C18] Choudhuri, Chiranjib; Ghosh, Abhishek; Mitra, Urbashi; Pamarti, Sudhakar; , "Robustness of xampling-based RF receivers against analog mismatches," Acoustics, Speech and Signal Processing (ICASSP), 2012 IEEE International Conference on , vol., no., pp.2965-2968, 25-30 March 2012
[C17] Wei Yao; Yiyu Shi; Lei He; Pamarti, S.; , "Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.20, no.1, pp.89-97, Jan. 2012
[C16] Nidhi, N.; Pin-En Su; Pamarti, S.; , "Open loop modulation techniques for wide bandwidth digital frequency synthesis," Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on , vol., no., pp.1-4, 7-10 Aug. 2011
[C15] Ghosh, A.; Pamarti, S.; , "A novel quantization noise-cancellation scheme in wideband D/A converters," Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on , vol., no., pp.1-4, 7-10 Aug. 2011 doi: 10.1109/MWSCAS.2011.6026467
[C14] Lee, F.S.; Salvia, J.; Lee, C.; Mukherjee, S.; Melamud, R.; Arumugam, N.; Pamarti, S.; Arft, C.; Gupta, P.; Tabatabaei, S.; Garlepp, B.; Hae-Chang Lee; Partridge, A.; Perrott, M.H.; Assaderaghi, F.; , "A programmable MEMS-based clock generator with sub-ps jitter performance," VLSI Circuits (VLSIC), 2011 Symposium on , vol., no., pp.158-159, 15-17 June 2011
[C13] Singhal, N.; Nidhi, N.; Ghosh, A.; Pamarti, S.; , "A 19 dBm 0.13µm CMOS parallel class-E switching PA with minimal efficiency degradation under 6 dB back-off," Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE , vol., no., pp.1-4, 5-7 June 2011 doi: 10.1109/RFIC.2011.5940714
[C12] D'Souza, Sandeep; Chang, Frank; Pamarti, Sudhakar; Agarwal, Bipul; Zarei, Hossein; Sowlati, Tirdad; Berenguer, Roc; , "A progammable baseband anti-alias filter for a passive-mixer-based, SAW-less, multi-band, multi-mode WEDGE transmitter," Circuits and Systems (ISCAS), 2011 IEEE International Symposium on , vol., no., pp.450-453, 15-18 May 2011 doi: 10.1109/ISCAS.2011.5937599
[C11] Rachid, Mansour; Pamarti, Sudhakar; Daneshrad, Babak; , "A novel reconfigurable alias interference cancellation technique for A-to-D conversion," Circuits and Systems (ISCAS), 2011 IEEE International Symposium on , vol., no., pp.1656-1659, 15-18 May 2011 doi: 10.1109/ISCAS.2011.5937898
[C10] Tzu-Chien Hsueh; Pamarti, S.; , "A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment," Custom Integrated Circuits Conference (CICC), 2010 IEEE , vol., no., pp.1-4, 19-22 Sept. 2010 doi: 10.1109/CICC.2010.5617472
[C9] Singhal, N.; Nidhi, N.; Pamarti, S.; , "A power amplifier with minimal efficiency degradation under back-off," Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on , vol., no., pp.1851-1854, May 30 2010-June 2 2010 doi: 10.1109/ISCAS.2010.5537819
[C8] Pin-En Su; Pamarti, S.; , "A 2-MHz bandwidth Delta-Sigma fractional-N synthesizer based on a fractional frequency divider with digital spur suppression," Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE , vol., no., pp.413-416, 23-25 May 2010 doi: 10.1109/RFIC.2010.5477398
[C7] Perrott, M.H.; Pamarti, S.; Hoffman, E.; Lee, F.S.; Mukherjee, S.; Lee, C.; Tsinker, V.; Perumal, S.; Soto, B.; Arumugam, N.; Garlepp, B.W.; , "A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.244-245, 7-11 Feb. 2010 doi: 10.1109/ISSCC.2010.5433937
[C6] Wei Yao; Yiyu Shi; Lei He; Pamarti, S.; Yu Hu; , "Worst case timing jitter and amplitude noise in differential signaling," Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design , vol., no., pp.40-46, 16-18 March 2009 doi: 10.1109/ISQED.2009.4810267
[C5] Tzu-Chien Hsueh; Pin-En Su; Pamarti, S.; , "A 3x3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation," Custom Integrated Circuits Conference, 2009. CICC '09. IEEE , vol., no., pp.121-124, 13-16 Sept. 2009 doi: 10.1109/CICC.2009.5280899
[C4] Farshchi, S.; Markovic, D.; Pamarti, S.; Razavi, B.; Judy, J.W.; , "Towards Neuromote: A Single-Chip, 100-Channel, Neural-Signal Acquisition, Processing, and Telemetry Device," Engineering in Medicine and Biology Society, 2007. EMBS 2007. 29th Annual International Conference of the IEEE , vol., no., pp.437-440, 22-26 Aug. 2007 doi: 10.1109/IEMBS.2007.4352317
[C3] Pamarti, S.; , "A Theoretical Analysis of Split Delta-Sigma ADCs," Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on , vol., no., pp.493-496, 27-30 May 2007 doi: 10.1109/ISCAS.2007.378678
[C2] Changbo Long; Sasank Reddy; Sudhakar Pamarti; Lei He; Tanay Karnik; , "Power-Efficient Pulse Width Modulation DC/DC Converters with Zero Voltage Switching Control," Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on , vol., no., pp.326-329, 4-6 Oct. 2006 doi: 10.1109/LPE.2006.4271858
[C1] Ken Chang; Pamarti, S.; Kaviani, K.; Alon, E.; Xudong Shi; Chin, T.J.; Jie Shen; Yip, G.; Madden, C.; Schmitt, R.; Yuan, C.; Assaderaghi, F.; Horowitz, M.; , "Clocking and circuit design for a parallel I/O on a first-generation CELL processor," Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International , vol., no., pp.526-615 Vol. 1, 10-10 Feb. 2005 doi: 10.1109/ISSCC.2005.1494101
JOURNALS
[J20] Singhal, N.; Zhang, H.; Pamarti, S.; , "A Zero-Voltage-Switching Contour-Based Outphasing Power Amplifier," Microwave Theory and Techniques, IEEE Transactions on , vol.PP, no.99, pp.1-11
[J19] Fitzgibbon, B.; Pamarti, S.; Kennedy, M.P.; , "A Spur-Free MASH DDSM With High-Order Filtered Dither," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.58, no.9, pp.585-589, Sept. 2011 doi: 10.1109/TCSII.2011.2161172
[J18] Singhal, N.; Nidhi, N.; Patel, R.; Pamarti, S.; , "A Zero-Voltage-Switching Contour-Based Power Amplifier With Minimal Efficiency Degradation Under Back-Off," Microwave Theory and Techniques, IEEE Transactions on , vol.59, no.6, pp.1589-1598, June 2011 doi: 10.1109/TMTT.2011.2131677
[J17] Pin-En Su; Pamarti, S.; , "A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation," Solid-State Circuits, IEEE Journal of , vol.46, no.3, pp.615-626, March 2011 doi: 10.1109/JSSC.2010.2099450
[J16] Tzu-Chien Hsueh; Pin-En Su; Pamarti, S.; , "A 3 ,\times, 3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation," Solid-State Circuits, IEEE Journal of , vol.45, no.8, pp.1522-1532, Aug. 2010 doi: 10.1109/JSSC.2010.2048136
[J15] Pin-En Su; Pamarti, S.; , "Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional- N PLLs," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.57, no.6, pp.1221-1230, June 2010 doi: 10.1109/TCSI.2009.2031746
[J14] Singhal, N.; Pamarti, S.; , "A Digital Envelope Combiner for Switching Power Amplifier Linearization," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.57, no.4, pp.270-274, April 2010 doi: 10.1109/TCSII.2010.2043399
[J13] Pin-En Su; Pamarti, S.; , "Fractional- N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.56, no.12, pp.881-885, Dec. 2009 doi: 10.1109/TCSII.2009.2035258
[J12] Pamarti, S.; , "Digital techniques for integrated frequency synthesizers: A tutorial," Communications Magazine, IEEE , vol.47, no.4, pp.126-133, April 2009 doi: 10.1109/MCOM.2009.4907419
[J11] Pamarti, S.; Delshadpour, S.; , "A Spur Elimination Technique for Phase Interpolation-Based Fractional- N PLLs," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.55, no.6, pp.1639-1647, July 2008 doi: 10.1109/TCSI.2008.916571
[J10] Pamarti, S.; , "The Effect of Noise Cross-Coupling on Time-Interleaved Delta-Sigma ADCs," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.55, no.6, pp.532-536, June 2008 doi: 10.1109/TCSII.2007.916794
[J9] Pamarti, S.; , "A Theoretical Study of the Quantization Noise in Split Delta-Sigma ADCs," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.55, no.5, pp.1267-1278, June 2008 doi: 10.1109/TCSI.2008.916554
[J8] Pamarti, S.; Galton, I.; , "LSB Dithering in MASH Delta-Sigma D/A Converters," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.54, no.4, pp.779-790, April 2007 doi: 10.1109/TCSI.2006.888780
[J7] Pamarti, S.; Welz, J.; Galton, I.; , "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.54, no.3, pp.492-503, March 2007 doi: 10.1109/TCSI.2006.887616
[J6] Alon, E.; Kim, J.; Pamarti, S.; Chang, K.; Horowitz, M.; , "Replica compensated linear regulators for supply-regulated phase-locked loops," Solid-State Circuits, IEEE Journal of , vol.41, no.2, pp. 413- 424, Feb. 2006 doi: 10.1109/JSSC.2005.862347
[J5] Pamarti, S.; Jansson, L.; Galton, I.; , "A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation," Solid-State Circuits, IEEE Journal of , vol.39, no.1, pp. 49- 62, Jan. 2004 doi: 10.1109/JSSC.2003.820858
[J4] Pamarti, S.; Galton, I.; , "Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol.50, no.11, pp. 829- 838, Nov. 2003 doi: 10.1109/TCSII.2003.819117
[J3] Pamarti, S.; , "A Theoretical Analysis of Split Delta-Sigma ADCs," Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on , vol., no., pp.493-496, 27-30 May 2007 doi: 10.1109/ISCAS.2007.378678
[J2] Changbo Long; Sasank Reddy; Sudhakar Pamarti; Lei He; Tanay Karnik; , "Power-Efficient Pulse Width Modulation DC/DC Converters with Zero Voltage Switching Control," Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on , vol., no., pp.326-329, 4-6 Oct. 2006 doi: 10.1109/LPE.2006.4271858
[J1] Ken Chang; Pamarti, S.; Kaviani, K.; Alon, E.; Xudong Shi; Chin, T.J.; Jie Shen; Yip, G.; Madden, C.; Schmitt, R.; Yuan, C.; Assaderaghi, F.; Horowitz, M.; , "Clocking and circuit design for a parallel I/O on a first-generation CELL processor," Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International , vol., no., pp.526-615 Vol. 1, 10-10 Feb. 2005 doi: 10.1109/ISSCC.2005.1494101