Research

This research involves implementing a Zero Voltage Switching (ZVS) Contour based PA. Theoretically the scheme achieves ZVS conditions over a 10dB range of output power by a simultaneous load and duty cycle modulation. Thus the PA can maintain its peak efficiency over a 10dB dynamic range of output power. A prototype 800 MHz, 19 dBm PA has been built in 0.13µm CMOS process to validate this concept. The PA achieves a peak drain efficiency is 23% and the peak PAE is 18%. The average drain and power added efficiencies while generating 6dB PMR, OQPSK signal with bandwidth up-to 20Mbps were found to be 20% and 15% respectively. The immediate plan is to design, have fabricated and test an IC which meets the WIMAX 4G spectrum requirements and enable a truly a high power, wide-bandwidth and efficient PA in CMOS. As before once implemented, the power amplifier has the potential to be used in a fully digital transmitter efficiently generating high PAPR and wide bandwidth modulated RF signals from digital base-band data with high fidelity.

Power amplification of wide bandwidth signals with high peak to average power ratio (PAPR) with sufficient efficiency and linearity continues to be a big challenge for RF PA designers. Conventional linear power amplifiers and recent attempts at digital power amplifiers fail to achieve high efficiency for wide bandwidth high PAPR signals. This research involves building a novel envelope D/A converter based digital polar power amplifier. The scheme uses N digital amplitude bits which switch on or off N low voltage switching parallel class E power amplifiers driven by the common constant envelope phase modulated signal. The outputs of the power amplifiers are combined using a transformer based voltage combiner. The envelope DAC based digital polar power amplifier is efficient, wideband and linear. Hence it can be used to generate high power, modulated, RF signals with high peak to average power ratio efficiently. Transistor-level circuit simulations in 0.l3um CMOS show that the PA achieves a error vector magnitude (EVM) < -25 dBm, adjacent channel power ratio (ACPR) < -40 dBc (Figure 1), and average drain efficiency of 40% while generating a 12dBm, 16.25 MHz, 8.9 dB PAR, 64 QAM signal. The immediate plan is to test the functionality and performance of the scheme on silicon. Once implemented, the power amplifier has the potential to be used in a fully digital transmitter efficiently generating high PAPR and wide bandwidth modulated RF signals from digital base-band data with high fidelity.

Polar and LINC are wireless RF transmitter architectures that allow the use of high efficiency nonlinear power amplifiers, and such architectures require a phase modulation path with a modulation bandwidth greater than 4 times the RF signal bandwidth. However, conventional phase modulation techniques for wireless transmitters have limited modulation bandwidth. This is because they generate the phase modulation signal within the phase-locked loop (PLL), such as an offset phase-locked loop (OPLL) or a fractional-N frequency synthesizer. As a result, the transmission bandwidth is limited by the PLL loop bandwidth and cannot have transmission rate greater than 1Mbps.To overcome this limitation, we use a phase modulation scheme that is achieved by properly selecting several available phases, which are generated by interpolating the PLL output. Besides, a quantization noise cancellation path is proposed to cancel out the phase quantization error that is introduced because of the finite available PLL phases. Since this modulation is implemented outside the PLL loop, the phase modulation bandwidth becomes independent of the PLL loop bandwidth. Thus, in preliminary simulation, the phase quantization can be reduced by about 9dB, and with a proper amplitude modulation, the transmitter can transmit 20MHz wide bandwidth 802.11g WLAN data that meets the -40dBc spectrum mask, as shown in the following figure.

The need to increase the throughput of a wireless network has led to modulation schemes which employ multi-level and OFDM modulation over a wider bandwidth channel. These wide-bandwidth signals typically have high PAPR. Using linear power amplifiers for such a system results in very low power efficiency, which in turn reduces the battery life in wireless applications. Polar transmitters can provide a power efficient solution for such a system by employing non-linear power amplifier in the transmit path. However, in a polar transmitter, the bandwidth of the amplitude and phase paths increases by 5x-10x of the RF signal bandwidth after combination. Hence, design solutions for power efficient and wide-band phase and amplitude modulators are required. Traditional approach for phase modulation pre-dominantly employs a phase-locked loop, which imposes limitations on the band-width of the transmitted signal. In order to increase the bandwidth beyond the PLL's loop bandwidth, digital open loop modulators are being investigated. Additionally, for low-power design without sacrificing linearity, this work will employ background calibration.

Ever-increasing data bandwidths have imposed unprecedented constraints on the performance of data-converters. In this research, we focus primarily on building very wideband ADC's, which can be configured easily in terms of bandwidth and resolution. We implement the ADC using a novel linearization scheme on a ring-VCO. The latter is an inexpensive way to effect quantization noise-shaping and hence mimics a conventional noise-shaping modulator but is plagued with problems of non-linearity. The scheme has been able to digitize signals having bandwidths to the tune of 25MHz with a resolution of ~12bits at a very low power consumption of 5-6mW thus guaranteeing an extremely competitive Figure of Merit (FoM) of roughly 25fJ/conv.step. Furthermore, the system has been found to be highly reconfigurable since it maintains this performance over a significantly wide bandwidth making it a potential candidate for software-defined, cognitive radio applications.

Differential-mode (DM) signaling has enabled multiple Gb/s data rates but at the expense of poor pin utilization (0.5 links/pin). Signaling systems exploit common-mode (CM) signaling resulting in a 50% higher pin utilization (0.75 links/pin). However, the aggregate data bandwidth of systems employing CM signaling remains low owing to inevitable interference between the DM and CM signals caused from on-die and PCB trace mismatches, package parasitic, signal time of flight differences and electromagnetic coupling. We proposed a technique based on the Code Division Multiple Access (CDMA) principle to suppress the signal crosstalk in multi-GHz multi-conductor signaling systems that employ simultaneous CM and DM signaling.The figure shows a simplified block diagram of the proposed CDMA-based signaling technique. As conventional CM signaling, three data links are realized in four wires: two DM links and a third link achieved by modulating the CMs of the two DM links in a differential manner. However, in the proposed technique, the CM signals are multiplied (spread) by the binary spreading signal, s(t), and the difference of the two extracted CMs is multiplied (de-spread) by an appropriately delayed version of s(t) followed by an integration receiver. The CDMA-like operations viz., spreading, de-spreading, and integration suppress the mode crosstalk by making the CM and DM signals orthogonal to each other.