News | September 16, 2024
$1.6 Million California State Grant to Enhance Engineering Pathways for Community College Students
Professor Greg Pottie (left) and Rick Wesel (right)
The UCLA Samueli School of Engineering, in collaboration with Cal State Polytechnic University Pomona, has secured a $1.6 million grant from the California Education Learning Lab. This grant will enhance the transition for community college students into four-year engineering programs and improve their academic and professional opportunities.
Professors Greg Pottie and Rick Wesel are co-principal investigators on the project. The project’s key efforts will include developing statewide bridge programs, improving credit transferability, and creating a comprehensive internship program.
Please see the press release.
Ozcan Lab published a new article in Nature Communications on early detection of Lyme disease
UCLA researchers, led by Professor Aydogan Ozcan, have developed a new technology for faster and simpler Lyme disease detection. This new method shortens diagnosis time, enhancing both accuracy and treatment speed.
Please see the full article and press release.
In collaboration with the University of Chicago, Ozcan Lab develop cost-effective diagnostic test for rapid cholesterol measurements
In a recent publication in ACS Nano, the Ozcan Lab, in collaboration with the University of Chicago, unveiled a new cost-effective diagnostic test for rapid cholesterol measurements. This innovative test combines two technologies and leverages machine learning to deliver quick and accurate results.
Please see the full paper and press release.
UCLA PhD Student Presents Groundbreaking Research on Hybrid Wiring Layers at Techcon
Vineeth Harish Unveils Innovative Paper on Fine Pitch Integration and Assembly: “Hybrid Wiring Layers for Fine Pitch Integration and Assembly“.
The ever-evolving landscape of semiconductor technologies demands innovative solutions to enhance integration, performance, and miniaturization. To meet these evolving needs, this paper explores the compelling necessity for advanced substrates that blur the conventional boundaries between integrated circuits (ICs) and packaging. A potential strategy in achieving this paradigm shift involves the incorporation of inorganic dielectric layers (SiO2) commonly used in CMOS BEOL fabrication on top of organic composite dielectric layers (ABF) commonly used in package substrate fabrication, specifically tailored for fine pitch routing and assembly on silicon core substrates. This paper details a comprehensive examination of the properties, fabrication techniques, and integration methodologies of both CMOS inorganic and traditional organic dielectric layers. Prior work has demonstrated for the first time, a 10um pitch solder-less Cu-Cu die to substrate assembly on organic build up film using an inorganic terminating layer on top of the organic polymer comprised of Si3N4 and SiO2. A low temperature ICP CVD process was used to deposit the dielectric, and the dual damascene process was used to form the Cu pillars for bonding.
Jaclyn Zhu Presents Breakthrough on Reducing Threshold Voltage Mismatch in Charge-Trap Transistors at TechCon
Jaclyn presented a groundbreaking approach to addressing threshold voltage mismatch on charge-trap transistors and proposed a novel mismatch reduction method called backgate programming. Promising data demonstrating the effectiveness of backgate programming was shown. Future work will focus on optimizing the technique, evaluating its retention, and exploring additional areas of application.
In Memoriam
We are deeply saddened by the passing of Professor Jimmy K. Omura on August 29, 2024. Born on September 8, 1940, in San Jose, California, Professor Omura was a prominent electrical engineer and information theorist.
He served as a professor of electrical engineering at UCLA for 15 years, where he made significant contributions to spread spectrum communications systems, and the Massey-Omura cryptosystem. He co-authored Principles of Digital Communication and Coding with Andrwe Viterbi and the Spread Spectrum Communications books.
Professor Omura was recognized with numerous accolades, including elevation to IEEE fellow in 1981, election as a member of the National Academy of Engineering in 1997, recipient of the IEEE Alexander Graham Bell Medal in 2005, and induction into the Silicon Valley Engineering Hall of Fame in 2009.
Our condolences go out to his family and all who were touched by his work.
Upcoming PhD Oral Defenses
9/19
Ph.D. Student: Jia Zhou
Time: 1-3pm
Room: Maxwell Room
11/13
Ph.D. Student: Jialin Dong
Time: 11am-1pm
Room: Faraday Room
10/2
Ph.D. Student: Luther Hwang
Time: 10am-12pm
Room: Maxwell Room
Job Opportunities
Design Verification Engineer at Apple
Do you have a passion for invention and self-challenge? This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Apple’s Silicon Engineering Group has embarked upon to-date. As a Design Verification Engineer on their team, you’ll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state-of-the-art Cellular SoCs!
You will have the opportunity to contribute to the verification effort of a set of complex SOCs delivering the Cellular solution. You will integrate multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM based test bench, implement effective coverage driven and directed test suites, deploy new tools and methodologies to deliver chips that are right-first-time. By collaborating with other product development groups across Apple, you can push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world!
Through this experience, you will learn all aspects of a large scale SOC design, Complex verification test benches, different types of SOC architectures, multiple high speed protocols, industry-standard low power architecture, best in class DV methodology, verification on accelerated platforms, knowledge on Cellular protocol, FW-HW interactions, complexities of multi-chip SOC debug architecture, etc.
Key Qualifications:
MS in EE or CS. Coursework in Digital Design, Computer Architecture, Object Oriented Programming, Networking Protocol. Programming experience in SystemVerilog or Python or C++ or Java.
Must be graduating by Dec ’24.
Please send your resume to j_lou@apple.com.
Newsletter Submissions
To be included in future newsletters, please send the latest news, awards, publications and any upcoming PhD oral defenses to the Chair’s assistant, Winda Mak, at wmak@seas.ucla.edu. Please include “newsletter submission” in the subject line. The ECE newsletters will be sent bimonthly on the first and third Mondays of the month. Please ensure all submissions are received by the Wednesday before distribution to be included in the newsletter.