Han Yan, Shi Bu, and Saptadeep Pal have won the very selective 2019 Qualcomm Innovation Fellowship. Only 13 proposals out of 115 were selected nationwide for this fellowship. All three are PhD candidates in the UCLA Electrical and Computer Engineering Department.
The Qualcomm Innovation Fellowship recognizes and rewards top PhD students across a range of technical research areas. Students apply and submit a proposal on any innovative idea of their choice. Winning students earn a one-year $100,000 fellowship and mentorship from Qualcomm engineers that help with the proposed research. Those who win exemplify Qualcomm’s core values of innovation, execution, and teamwork.
Han Yan and Shi Bu
Han Yan’s work is conducted at the UCLA Cognitive Reconfigurable Embedded Systems (CORES) lab under his advisor Prof. Danijela Cabric. Shi Bu’s work is conducted at the UCLA Signal Processing and Circuit Engineering (SPACE) group under his advisor Prof. Sudhakar Pamarti. Together their research proposal is titled “A Wideband Frequency-Channelized ADC Using Time-Varying Circuits and Adaptive Digital Control.” This research focuses on developing analog-to-digital converters (ADCs) with GHz bandwidth and high resolutions for direct radio-frequency (RF) data acquisition.
Han and Shi’s research would enable signal aggregation from multiple communication bands/standards using only a single RF link. It would also allow for radios to be “upward compatible” with new communication protocols, future-proofing against modifications in the future. If successful, this research would reduce the complexity and power consumption of radios in mobile terminals, impacting strongly wireless communication in the era beyond 5G.
To achieve this, Han and Shi propose a frequency-channelized ADC architecture with three key innovations. First, they will intentionally use time-varying circuits as sharp RF filters to channelize the spectrum, which will handle “peaky” spectrum in aggregated wireless communications while the time-varying nature while help reconfiguration of the RF filters. Second, they will program the sub-ADCs to accommodate the dynamic range in their respective channels to fully adapt to the spectrum environment at will with minimum power. Third, they will develop new background calibration algorithms that will use received signals to handle circuits with non-idealities after reconfiguration. Together these attributes make up an ADC that has the potential to significantly advance the field of high speed ADC designs.
Learn more about Han’s research at http://cores.ee.ucla.edu
Learn more about Shi’s research at http://www.seas.ucla.edu/spgroup/index.html
Saptadeep Pal earned his B. Tech in Electrical Engineering from Indian Institute of Technology Patna in 2015 and his M.S. in Electrical Engineering from UCLA in 2017. His proposal is titled “Revolutionizing Large-Scale Graph Processing using Waferscale Architecture.” His work is conducted at the NanoCAD laboratory under his advisor Prof. Puneet Gupta and at the Center for Heterogeneous Integration and Performance Scaling (CHIPS) under his co-advisor Prof. Subramanian S. Iyer. He has also collaborated with Prof Rakesh Kumar from University of Illinois at Urbana-Champaign and his student Matthew Tomei, who co-wrote the proposal.
Saptadeep’s research focuses on high performance computer architecture and design of waferscale systems. This tackles the needs of highly data dependent applications such as AI, graph processing, and medical image processing by aiming to develop parallel hardware that can supply high throughput and energy efficiency.
Parallel hardware requires low overhead communication between different computing nodes, but that overhead has been quickly increasing and forming a significant bottleneck in performance scaling. Saptadeep aims to address this issue by building new highly parallel architectures on a novel interconnect fabric (Silicon Interconnect Fabric) which would allow for 5-10 times higher interprocessor bandwidth and up to 50 times lower energy usage per bit. This would allow for waferscale processors to be built that are 40-50 times larger than current processors. Saptadeep is currently working on architecting a waferscale graph processor. Initial results show that such a processor can have at least 20 times performance benefit over conventional systems. Efficient graph processing can potentially open up many avenues in data analytics and scientific computing which are currently out-of-reach.
Saptadeep’s team is trying to build the world’s first waferscale prototype processor system using Si-IF technology. Learn more about his research at http://nanocad.ee.ucla.edu and https://www.chips.ucla.edu