Charge-Trap Transistors for Neuromorphic Computing

Speaker: Xuefeng Gu
Affiliation: Ph.D. Candidate - UCLA

Abstract:  As the demand for energy-efficient cognitive computing keeps increasing, the conventional von Neumann architecture is called into question. Brain-inspired, or neuromorphic computing has been extensively investigated in the past three decades because of its distributed memory/processors and massive connectivity, which promise low-power operation. One critical device in such a system is the synapse – a local memory which stores the connectivity between neurons. Many devices, such as resistive memory, phase-change memory, ferroelectric field-effect-transistor, and flash memory have been suggested as a candidate for analog synapses. In this work, a CMOS-only and manufacturing-ready candidate – the charge-trap transistor (CTT) is investigated.

In the first part, the analog programming characteristics of CTTs most pertinent to neuromorphic applications will be presented. In particular, the analog retention, the fine-tuning of individual CTTs, the device variation, and the spike-timing dependent plasticity will be discussed.  In the second part, two algorithms for unsupervised learning, namely, winner-takes-all (WTA) clustering and temporal correlation detection, are investigated, using CTTs as the analog synapses. For each algorithm, the feasibility of hardware implementation using CTTs as the analog synapses is first studied and system performance evaluated using experimentally measured CTT characteristics. Experimental demonstration is next presented using custom-built CTT arrays in 22 nm fully depleted silicon-on-insulator (SOI) technology.

Finally, the use of CTTs for analog synapses in an inference engine is considered. The fine-tuning of CTT weights in an array setting is first examined as it is anticipated to be different from that of discrete devices because of the half-selection and thermal disturbance by adjacent cells. The achieved standard deviation of the difference between the target and the actually programmed weight is as low as < 6% of the dynamic range. The use of the programmed CTT array as a dot product engine is demonstrated. In addition, the performance of an inference engine using CTT as analog synapses is discussed.

Biography:  Xuefeng Gu received the B.E. in Information Engineering from Southeast University and M.S. in Electrical Engineering from the University of California, Los Angeles, in 2011 and 2013, respectively. He is currently pursuing a Ph.D. in Electrical and Computer Engineering at UCLA. His research mainly focuses on the characterization of the charge-trap transistor and its application in various aspects of neuromorphic computing systems. In 2016, he interned with IBM working on product-technology interaction in 14-nm FinFET technology.

For more information, contact Prof. Subramanian Iyer ()

Date(s) - Nov 27, 2018
10:00 am - 12:00 pm

E-IV Maxwell Room #57-124
420 Westwood Plaza - 5th Flr. , Los Angeles CA 90095