CMOS-Compatible Logic Embedded High-K Charge-Trap Transistor (CTT) Based Multi-Time-Programmable-Memory

Speaker: Toshiaki Kirihata
Affiliation: Design Manager, GlobalFoundries

Abstract:  Embedded non-volatile memory (NVM) technologies are gaining significant prominence, especially in redundancies for 3D memories, and firmware for micro-controllers. Unlike standalone high density NVMs that are mainly used for storage, these embedded applications do not need ultra-high density or endurance, instead need (i) 100% logic compatible and scalable process to FinFET with zero mask adder, (ii) logic compatible operational voltage, (iii) high-temperature operation, and (iv) hardware security. This talk focuses on the design and implementation of an embedded Multi-Time-Programmable-Memory (MTPM) using Charge-Trap Transistor (CTT) with no added process complexity. Logic FETs with high-k dielectric gate oxide are used as storage elements with logic-compatible programming voltages. Over-write protection and block-write algorithm have been employed to improve the memory performance. Macro functionality and multi-time programmability have been demonstrated in 32nm, 22nm SOI and 14nm bulk FinFET technologies. High temperature stress results show a projected data retention of ~10 years at 125oC. Future scope for this memory includes endurance improvement using forming technique, and realization of a unified memory supporting One-Time-Programmable-Memory (OTPM), self-destructive MTPM and Physically Un-clonable Fuse modes of operation.

Biography: Toshiaki Kirihata, senior member of the IEEE, received his B.S. and M.S. degrees in Precision Engineering from Shinshu University, Nagano, Japan, in 1984 and 1986, respectively. In 1986, he joined IBM Research, Tokyo Research Laboratory, and worked on high-speed DRAM design development. In 1996, he transferred to IBM Research, T. J. Watson Research Center, where he worked on research and development for high-density DRAMs. In 2000, he joined the IBM Semiconductor Research and Development Center, East Fishkill, where he has been working on the development of high performance embedded DRAMs and embedded 3D memories as a design manager. Mr. Kirihata presented papers at the ISSCC 1998, 1999, 2001, and 2004 conferences. He received the Lewis Winner outstanding paper award on the ISSCC paper entitled “A 500MHz Random Cycle, 1.5ns Latency, SOI Embedded DRAM macro Featuring a Three Transistor Micro Sense Amplifier”. He is currently a design manager for GLOBALFOUNDRIES.  Mr. Kirihata is an IEEE CICC committee member on memory, and served as a Memory session chair in the year 2014. His research interests include high performance embedded DRAM, embedded non-volatile memory, 3D memory, and hardware security. He is one of the authors of “CMOS Processors and Memories” (Springer, 2010) and “Circuit for Emerging Applications” (CRC Press, 2014), contributing to the chapters on eDRAM and intrinsic chip ID using eDRAM, respectively.

For more information, contact Prof. Subramanian S. Iyer ()

Date/Time:
Date(s) - Nov 07, 2016
3:00 pm - 4:00 pm

Location:
E-IV Tesla Room #53-125
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095