Co-optimization of Restrictive Patterning Technologies and Design

Speaker: Yasmine Badr
Affiliation: Ph.D. Candidate - UCLA

Abstract:  As the semiconductor industry strives to find novel technology scaling methods, the advanced technologies (sub-15nm) have become restrictive to the design, affecting design metrics like area, delay, and power. Thus, the semiconductor industry has resorted to Design and Technology Co-Optimization (DTCO) in order to develop technologies with desirable characteristics for both the design and the fabrication.

In the first part of this dissertation we propose computational methods to address challenges of developing a new technology. First we propose Chip-DRE, a framework for chip-level evaluation of design rules which considers the interaction of design rules with performance and routing congestion. Second, we propose Pattern-DRE, a framework for pattern-based assessment of design rules which is essential in sub-wavelength lithography.

In the second part of the dissertation, we focus on algorithms to enable Directed Self-Assembly (DSA), which is a disruptive technology with very attractive scaling potential but with unique constraints on the design. We first propose DSA-Pathfind, an optimal path-finding framework for DSA for via layers. Then we propose scalable algorithms for the integration of DSA and Multiple Patterning.

Finally, we propose and evaluate the use of a buried interconnect layer as a technology scaling booster.

Biography:  Yasmine Badr received her B.S. and M.S. in Computer Engineering in 2009 and 2012 respectively from Cairo University in Egypt. Before joining UCLA, she was an Assistant Lecturer in the Computer Engineering Department at Cairo University and a part-time Research Engineer at Mentor Graphics, Egypt.

For more information, contact Prof. Puneet Gupta ()

Date/Time:
Date(s) - Jun 30, 2017
11:00 am - 2:00 pm

Location:
E-IV Tesla Room #53-125
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095