Design Considerations for Power Efficient Continuous-time Delta Sigma Analog-to-Digital Converters

Speaker: Prof. Shanthi Pavan
Affiliation: Indian Institute of Technology, Madras

Abstract: Continuous-time Delta-Sigma Modulators (CTDSMs) are a compelling choice for the design of high-resolution analog-to-digital converters. Many delta-sigma architectures have been published (and continue to be invented). This leaves the designer with a bewildering array of choices, many of which seem to pull in opposite directions. Further, it is often difficult to make a clear comparison of various architectures, as they have been designed for dissimilar specifications, by different design groups, and in different technology nodes. This talk examines various alternatives for the design of power efficient single-loop continuous-time delta sigma converters.

Biography:  Shanthi Pavan is currently a Professor of Electrical Engineering at the Indian Institute of Technology, Madras. His research interests are in the areas of high-speed analog circuit design and signal processing. He has received many awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award (2009), the Shanti Swarup Bhatnagar Award (2012). He has been the Editor-in-Chief of the IEEE Trans. on Circuits and Systems: Regular Papers and is the author of Understanding Delta-Sigma Data Converters (Second Edition), with Richard Schreier and Gabor Temes. He is a fellow of the IEEE. 

For more information, contact Prof. Sudhakar Pamarti (spamarti@ucla.edu)

Date/Time:
Date(s) - Apr 13, 2018
1:00 pm - 2:00 pm

Location:
EE-IV Shannon Room #54-134
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095