Design, Evaluation and Co-optimization of Emerging Devices and Circuits

Speaker: Shaodi Wang
Affiliation: Ph.D. Candidate - UCLA

Abstract: The continued push for traditional Silicon technology scaling faces the main challenge of non-scaling power density. Exploring alternative power-efficient technologies is essential for sustaining technology development. Many emerging technologies have been proposed as potential replacement for Silicon technology. However, these emerging technologies need rigorous evaluation in a circuit and system to identify their value prior to commercial investment. We have developed evaluation frameworks covering emerging Boolean logic devices, memory devices, memory systems, and integration technologies. The evaluation metrics are in terms of delay, power, and reliability. According to the evaluation results, the development of emerging logic devices is still far from being able to replace Silicon CMOS, but magnetic random access memory (MRAM) is identified as a promising technology showing benefits in performance and energy-efficiency.

As a specific example, we co-optimize MRAM with application circuits and systems. Optimized MRAM write and read design can significantly improve the system performance. We have proposed magnetic tunnel junction (MTJ) based process and temperature variation monitor, which enables variation-aware MRAM write and read optimization. We have also proposed utilizing negative differential resistance (NDR) to enable fast and energy-efficient write and zero-disturbance read for resistive memories including MRAM. In addition, we also design and adapt MRAM technology into low-power stochastic computing system to improve energy-efficiency. To further improve the stochastic computing system, a promising VC-MTJ based true random stochastic bitstream generator is proposed and utilized.

Biography:  Shaodi received his B.S. degree from Peking University, China. In 2011, he joined the University of California, Los Angeles, where he is currently Ph.D. Candidate in the NanoCAD lab at Department of Electrical Engineering, UCLA. His research interests include emerging memory and device technology, circuit, and system-level design, evaluation and optimization.

For more information, contact Prof. Puneet Gupta ()  

Date/Time:
Date(s) - Apr 19, 2017
12:00 pm - 2:00 pm

Location:
E-IV Faraday Room #67-124
420 Westwood Plaza - 6th Flr., Los Angeles CA 90095