Speaker: Prof. Mingoo Seok
Affiliation: Columbia University
Abstract: The Internet of Things (IoT) technology has been permeating various parts of our life. Since such IoT devices start to produce an enormous amount of data, it is important to extract key information from the data at low cost. For this, engineers and scientists have been trying to leverage the recent advances in artificial intelligence (AI) and machine learning (ML). The current practice is to upload the data to a data-center, which then performs the complex algorithms such as convolutional neural network algorithms on it. However, this paradigm is not scalable for i) large energy cost and ii) latency of data round-trip between an IoT device and a data-center and iii) the privacy and security concern of data uploaded in a data-center. Under my direction, the VLSI Design Lab at Columbia University (VLSIDL) has been striving to enable a new paradigm, where an IoT device locally performs AI and ML algorithms, or at least a critical portion of them, and thus substantially reducing the data footprint to/from a data center. Indeed, AI and ML algorithms are computationally very complex. To perform them locally in a typically resource-constrained IoT device, we need innovative computing architectures. My lab focuses to create i) post Moore’s law digital architecture for neural network workloads and ii) analog-mixed-signal computing architecture for always-on classification, to enable improvement in energy-efficiency, performance, and robustness. My lab also focuses to create new power supply architecture, which those emerging computing architectures demand. In this talk, we will introduce several of them with the test-chip prototypes and measurements.
Biography: Mingoo Seok is an associate professor of Electrical Engineering at Columbia University. He received the B.S. from Seoul National University, South Korea, in 2005, and the M.S. and Ph.D. degree from the University of Michigan in 2007 and 2011, respectively, all in electrical engineering. His research interests are various aspects of VLSI circuits and architecture, including ultra-low-power integrated systems, cognitive and machine-learning computing, adaptive technique for the process, voltage, temperature variations, and transistor wear-out, integrated power management circuits, event-driven controls, and hybrid continuous and discrete computing. He won the 2015 NSF CAREER award and 2019 Qualcomm Faculty Award. He is the technical program committee member for multiple conferences including IEEE International Solid-State Circuits Conference (ISSCC). He has been as an associate editor for IEEE Transactions on Circuits and Systems Part I (TCAS-I) (2014-2016), IEEE Transactions on VLSI Systems (TVLSI) (2015-present), IEEE Solid-State Circuits Letter (SSCL) (2017-present), and as a guest associate editor for IEEE Journal of Solid-State Circuits (JSSC) (2019).
Date(s) - Dec 04, 2019
11:00 am - 12:00 pm
EE-IV Shannon Room #54-134
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095