Essential Blocks for Low-Power Applications: DPLL and Energy Harvesting Circuit

Speaker: Chien-Heng Wong
Affiliation: Ph.D. Candidate - UCLA

Abstract:  As wireless sensor networks and internet of things gain traction in industrial, medical and consumer applications, low-voltage low-power and energy harvesting circuits become a key enabling technology where direct power is impractical or battery replacement is difficult.

Digital phase-locked loops (DPLL) have drawn increasing attention recently due to advantages in employing area/energy-efficient digital cells. A compact low-supply-voltage yet low-noise bang-bang DPLL is proposed. The bang-bang phase detector in this work is based on a dynamic double-tail latch which enables high time-to-voltage gain and low input-referred noise under tight power supply headroom. The ring-based digitally-controlled oscillator (DCO) is made of multiple gm-controlled delay units and a constant-gm-biased current digital-to-analog converter. By combining these two blocks, the DCO can now better tolerate supply noise and process variations. A prototype DBBPLL has been implemented in 28nm CMOS process with compact die area of 0.014mm2. When operating at 2.6GHz, it consumes 2.9mW with 0.75V supply and achieves low in-band phase noise of -105dBc/Hz.

Energy harvesting circuit is another critical block in low-power applications while off-chip passive components occupying large PCB area are unavoidable. A fully integrated dual source adaptive thermoelectric and RF energy harvesting circuit is presented. Its boost oscillator, rectifier and boost converter all operate at RF frequency to make inductor and capacitor integration feasible. The oscillator Gm adaptive bias reduces current consumption at higher voltage while assists startup at lower voltage. The RF input signal further reduces startup voltage through Q-enhanced amplification and super-regenerative mode. Implemented in 28nm CMOS, it achieved a self-startup voltage of 110mV without RF input and 85mV at -16dBm input. The boost converter power conversion efficiency (PCE) is 25% and the harvester overall PCE is 10%.

Biography: Chien-Heng Wong is currently a Ph.D. candidate in the Department of Electrical and Computer Engineering under the mentorship of Professor Frank Chang. He received B.S. and M.S. degree from National Taiwan University in 2008, and 2011.

For more information, contact Prof. Frank Chang ()

Date/Time:
Date(s) - Apr 04, 2018
4:00 pm - 5:30 pm

Location:
E-IV Maxwell Room #57-124
420 Westwood Plaza - 5th Flr. , Los Angeles CA 90095