Speaker: Prof. Yogesh S. Chauhan
Affiliation: Indian Institute of Technology Kanpur (IITK)

IEEE Distinguished Lecturer Series

Abstract: The ongoing scaling of CMOS technology is now reaching its limit, due to supply voltage reduction being restricted by the subthreshold swing (SS) of 60mV/decade achievable at room temperature owing to Boltzmann transport of the charge carriers. Concept of negative capacitance proposed to achieve a sub-60mV/decade SS is currently seen as one of the potential solutions to the problem. A “negative capacitance transistor (NCFET)” employs a ferroelectric material in the gate stack of a FET providing a negative capacitance and thereby an “internal voltage amplification” at the gate of the internal FET which helps in reducing SS. Several experiments have successfully demonstrated an improved SS with the bulk MOSFET, FinFET, and 2D FETs. The improvement in subthreshold characteristics is also accompanied with the advantage of an increased ON current relative to the reference FET as has been observed both in simulation studies and experiments. In this talk, I will discuss the physics and modeling of various NCFET structures and impact of this new transistor on circuits including processors.

Biography:  Yogesh Chauhan is an associate professor at IIT Kanpur. He was with IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012. He is the developer of several industry standard models: ASM-GaN-HEMT model, BSIM-BULK model (formerly BSIM6), BSIM-CMG model and BSIM-IMG model. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs.

He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the member of IEEE-EDS Compact Modeling Committee. He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and Vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences. He has served in the technical program committees of IEDM, SISPAD, ESSDERC, EDTM, and VLSI Design Conference.

For more information, contact SivaChandra Jangam at sivchand@ucla.edu.

Date/Time:
Date(s) - Jun 13, 2019
9:30 am - 11:00 am

Location:
E-IV Maxwell Room #57-124
420 Westwood Plaza - 5th Flr. , Los Angeles CA 90095