Integration of Voltage-Controlled Spintronic Devices in CMOS Circuits

Speaker: Hochul Lee
Affiliation: Ph.D. Candidate - UCLA

Abstract: Spintronics is an emerging field that studies the properties of electron spin and discovers the methods to detect and manipulate its associated magnetic moment in a solid-state device. Utilization of spintronic devices has been considered as a possible alternative for beyond CMOS technology. One of the most promising spintronic devices is a magnetic tunnel junction (MTJ) that has attracted the attention of academia and industry owing to its remarkable characteristics such as non-volatility, virtually unlimited endurance, and CMOS compatibility. Although the discovery of the spin-transfer torque (STT) and spin Hall effect (SHE) allow achieving a nanosecond switching speed, these current-driven switching methods inherently cause a significant ohmic loss. Recently, a voltage-controlled effect has been utilized to mitigate the energy issue by drastically reducing ohmic dissipation during switching in a noble memory architecture called magnetoelectric RAM (MeRAM). In addition to achieving high-energy efficiency, voltage-induced switching leads to further improvement in terms of density and switching speed, opening the door to new possibilities of next generation low-power and high-speed system architectures.

            In this talk, we explore the characteristics of voltage-controlled magnetic anisotropy (VCMA) effect driven precessional switching based on an MTJ macrospin compact model including the VCMA effect in its built-in Landau-Lifshitz-Gilbert (LLG) equation, predicting required bias conditions for switching with the low write error rate (WER). Furthermore, we demonstrate a wide variety of spintronics-CMOS circuits utilizing unique features of voltage-controlled MTJ in which the performances of the proposed circuits are improved by an order of magnitude, especially, in terms of energy and area. Also, we develop several practical design techniques to improve the reliability of the read and write operations in MeRAM and demonstrate a synchronous 4Kbit MeRAM macro design based on IBM 130 nm technology.

Biography:  Hochul Lee is currently a Ph.D. candidate of Device Research Lab (DRL, Prof. Kang L. Wang) in UCLA where he is exploring novel schemes for energy-efficient spintronics devices in memory and logic applications. He received the B.S and M.S degree in electrical engineering from Korea University in 2005 and Seoul National University in 2007, respectively. He studied on random telegraph noise (RTN) of nano-scale devices for his M.S research and received a fellowship from the Korea foundation for advanced studies. After graduation, he had worked in the memory division of Samsung Electronics as a NAND flash memory circuit designer from 2007 to 2012. Also, he has led a circuit design team in Inston, Inc. from 2015 to 2017 to demonstrate prototypes of magneto-electric random-access memory (MeRAM). Hochul has more than seven years of memory circuit design experience and seven years of research on electronic/spintronic devices in academia resulting in 19 journal issues and the filing of three patents.

For more information, contact Prof. Kang L. Wang ()

Date(s) - Sep 05, 2017
1:00 pm - 3:00 pm

E-IV Tesla Room #53-125
420 Westwood Plaza - 5th Flr., Los Angeles CA 90095