Speaker: Haobo Wang
Affiliation: Ph.D. Candidate - UCLA
Abstract: Modern Flash memory based data storage systems have enabled the wide spread of high performance computation platforms, from smartphones to intelligent vehicles to data centers. As the keystone of computation platforms, such storage systems are one of the bottlenecks for improving the baseline reliability and performance of computation. The design of Flash-based storage usually revolves around four metrics: lifetime, reliability, latency, and throughput. In this dissertation, I focus on optimizing Flash-based storage systems at the physical layer to address the four metrics. I propose two types of optimizations that (Part 1) extend the lifetime of Flash memory by adaptively scaling the write threshold voltages, and (Part 2) improve the throughput and latency of modern storage systems by exploiting the parallelization of short-blocklength error correction codes with incremental redundancy.
In the first part, I will present the novel concept of dynamically voltage allocation (DVA) for Flash memory. Flash memory suffers reduced reliability as the number of program/erase (P/E) cycles increases, thus has a limited lifetime. DVA scales the write threshold voltages of Flash memory adaptively, using lower voltages at the beginning of the lifetime, and gradually increases the scaling to combat the effect of accumulated wear-out from P/E cycling. The proposed algorithm significantly increases the lifetime of the device.
In the second part, I will present the novel design of error correction with incremental redundancy without feedback. Modern storage systems often require high throughput, high reliability and low latency. Traditional variable-length (VL) codes with feedback have demonstrated to provide high throughput and reliability. The new design reinterprets the results for VL codes with feedback using ergodicity, by encoding the incremental redundancy of multiple VL codewords to a common pool of redundancy. The removal of feedback allows storage systems to benefit from the performance of a feedback scheme with a feedforward design. The decoder of the new design exploits the low complexity of short-blocklength decoders and the parallelization structure to reduce latency. The proposed error correction scheme approaches the throughput of corresponding VL codes with feedback.
Biography: Haobo Wang is currently a Ph.D. candidate in the Department of Electrical and Computer Engineering at UCLA. He is a member of the Communications System Laboratory under the mentorship of Professor Richard Wesel. His research focuses on developing advanced communication theory for high-speed communication systems. Haobo Wang received the B.S. degrees from Tsinghua University, Beijing, China in 2012, and the M.S. degree from the University of California at Los Angeles (UCLA), Los Angeles, California in 2014, all in Electrical Engineering.
For more information, contact Prof. Richard Wesel (email@example.com)
Date(s) - Aug 17, 2018
2:00 pm - 4:00 pm