Revisit Die-stacking Architecture: Are we there yet?

Speaker: Yuan Xie
Affiliation: Professor, UCSB

Abstract: In this talk, I will first give an overview of research activities in Scalable Energy-efficient Architecture Lab (SEAL) http://seal.ece.ucsb.edu/, especially on the design and architecture with emerging three-dimensional integrated circuits (3D ICs) and emerging memory technologies.

I will then focus on 3D die-stacking architecture, review the progress in research for die-stacking CPU/GPU architecture, discuss the design challenges and opportunities, and finally a brief discussion on the recent announced commercial die-stacking GPU architecture.

Biography: Yuan Xie is a Professor at UC Santa Barbara (UCSB).  He received his Ph.D. from Princeton University, and then joined IBM Microelectronics as an advisory engineer. From 2003 to 2014, he was with Penn State as Assistant/Associate/Full Professor. He also took on-leave and worked with AMD between 2012 and 2013, to help AMD on 3D die-stacking projects. His research interests include EDA/architecture/VLSI, and he has published more than 200 papers in IEEE/ACM venues. He was elevated to IEEE Fellow for contributions in design automation and architecture for 3D ICs. Professor Xie is currently the Editor-in-Chief for ACM Journal of Emerging Technologies in Computing Systems.

For more information, contact Prof. Puneet Gupta ()

Date/Time:
Date(s) - Feb 18, 2016
1:00 pm - 3:00 pm

Location:
E-IV Faraday Room #67-124
420 Westwood Plaza - 6th Flr., Los Angeles CA 90095